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VX2745

Coming Soon

64 Channel 16 bit 125 MS/s Digitizer with Programmable Input Gain

Features

  • 16 bit @ 125 MS/s ADC
  • 64 analog inputs, differential or single-ended, programmable input range, individual DC offset adjustment
  • Four 2mm 40-pin header connectors
  • Wide range of applications (from Neutrino Physics & Dark Matter to Nuclear and Particle Physics to Spectroscopic Imaging)
  • Suited for signals from Semiconductor Detectors cupled with CSPs (Si, HPGe) or scintillators coupled with PMTs (NaI, CsI)
  • On-board firmware selection for different aquisition modes:
    – Scope mode (simultaneous raw waveform acquisition
    on common trigger)
    – DPP-PHA mode (pulse height and time acquisition on
    independent channel self-triggers)
    – Predisposition for other planned algorithms: QDC, PSD,
    CFD, DAW, ZLE, etc.
  • Multi-board synchronization and system building capabilities
  • Front panel fully programmable I/Os (4 LEMO TTL/NIM and 16 LVDS)
  • Special 125MS/s 14bit DAC output (LEMO) for signal inspection or trigger sum
  • On-board Xilinx Zynq® UltraScale+™ FPGA with embedded Linux-based ARM processor
  • 2.5GB of Total Acquisition memory (DDR4)
  • USB 3.0 type-C and 1/10 Gigabit Ethernet or optional CONET (CAEN Daisy Chainable Optical Link Protocol Coming Soon) interfaces
  • Fully supported by CoMPASS and WaveDump2 readout software
  • SDK for embedded Linux processor and host PC
  • Open FPGA

Overview

The VX2745 Digitizer is a 64-channel digital signal processor for radiation detectors in a VME64X form factor. It offers not only waveform digitization and recording but also Multi-Channel Analysis for nuclear spectroscopy using Silicon strip, segmented HPGe, Scintillation detector with PMTs, Wire Chambers, and others.

The VX2745 can perform pulse height measurements (PHA), constant fraction timing (CFD), charge integration (QDC) and pulse shape discrimination (PSD) independently for each of the 64 channels.
Each channel of the module digitizes the analog input, that can be the signal coming from a physics detector, with a 16 bit, 125 MS/s ADC. The sampled data are used to initiate the digital pulse processing sequence, managed in the FPGA at the firmware level. Different firmware types can be selected via software, according to the specific setup and acquisition mode.

  • Common trigger: all channels acquire simultaneously with a common trigger. The trigger can be fed externally or generated by a combination of individual channel discriminators. This mode is mainly intended for the acquisition of waveforms, like a digital oscilloscope. Options for zero suppression are available to remove not significant data.
  • Independent trigger: suited for trigger-less applications, where no global trigger is needed but each channel acquires waveforms upon its self-trigger which fires through a digital discriminator, independently of the others.
  • DPP: real-time processing in the FPGA allows for the extraction of physical parameters from the waveform (e.g. pulse height, charge, timestamp, PSD), well suited for high counting rate applications. It is yet possible to save both raw waves and parameters.

A template of the firmware is available for customers who want to personalize the acquisition to implement custom algorithms for pulse processing in the open FPGA. The user can have control of the data output information and customize the trigger logic to get several combinations of self-triggers and I/O signals to validate or discard the events.
Custom software can run on the onboard CPU for data reduction and analysis. Multi-board synchronization can be implemented via backplane or front panel easy-cabling options.
Fast readout options are available, like Ethernet 1Gb or 10Gb, USB3.0 (tested up to 280 MB/s), and optical link (CAEN Daisy Chainable Optical Link Protocol Coming Soon).

Technical Specifications

GENERAL
Form Factor

1-unit wide VME64X 6U
▪ 1-unit wide VME64 6U
▪ Desktop

Weight

VX2745: 642 g

Valid also for B versions

 

  

ANALOG INPUT
Channels

64 channels
Differential on 2745 versions
Single-ended on 2745B versions

Impedance
50 Ω single-ended
100 Ω differential

Connector

Four 2mm 40-pin header male
Input adapters available

Programmable Full Scale Range
From 0.4 to 4 Vpp

Bandwidth (-3 dB)

50 MHz

Offset
Individual offset adjustable in the ±1.25V range

  

DIGITAL CONVERSION
Resolution

16 bits

Sampling Rate

125 MS/s (simultaneously on each input)

 

  

SYSTEM PERFORMANCE
ENOB

11.7 (Typ.)

RMS

3.9 LSB (≃ 120 µV) typical RMS

 

  

DIGITAL I/O
 CLK-IN

Two differential pairs:
▪ CLK: reference clock signal
▪ SYNC: synchronization signal (start/stop, T0, etc.)
AC-coupled LVDS, ECL, PECL, LVPECL, CML
Zdiff = 100 Ω
2.54mm 4-pin AMPMODU Mod II male connector

AC-coupled LVDS, ECL, PECL, LVPECL, CML
Zdiff = 100 Ω
2.54mm 4-pin AMPMODU Mod II male connector

CLK-OUT

Same functionalities as CLK-IN
Daisy chainable in multi-board synchronization
LVDS
2.54mm 4-pin AMPMODU Mod II male connector

LVDS I/O

16 differential pairs
Software programmable I/O (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.)
LVDS
Zdiff = 100 Ω (when set as inputs)
2.54mm 34-pin AMPMODU Mod II male connector

TRG-IN/TRG-OUT/GPIO/S-IN

General purpose I/Os
Software programmable (trigger, gate, veto, busy, etc.)
Sigle-ended TTL/NIM

  • TRG-IN/S-IN internally terminated with 50 Ω (Zin = 50 Ω)
  • TRG-OUT requires Rt = 50 Ω
  • GPIO as Input must be terminated with 50 Ω
  • GPIO as TTL Output requires Rt = 50 Ω
  • GPIO as NIM Output requires Rt = 50 Ω or 25 Ω

LEMO 00 male connector

   

 

DAC OUT

DAC output for signal inspection, pulse generation, majority level
14-bit Digital-to-Analog Converter (DAC)
125MS/s Update Rate
±1 V @ 50Ω load; ±2 V @ hi-Z load Output Range
LEMO 00 male connector

ACQUISITION MEMORY

2.5 GB total DDR4 memory size (20.971 MS/ch) divisible in multiple buffers
Maximum record length: ≃ 168 ms @ 125 MS/s (total memory size divided by 2)1

1 Value referred to the Scope firmware (minimum of two buffers admitted)

 

TRIGGER MODES
  • Common: all channels acquire simultaneously with the trigger (software, external or logic combination of self-triggers)
  • Individual: each channel acquires independently with its self-trigger
  • Correlated: the individual self-trigger of each channel is validated by the coincidence/anticoincidence logic between other self-triggers and/or external I/Os
SYNCHRONIZATION
Clock Propagation

Typical 62.5MHz frequency distributed by daisy chain
through CLK-IN/CLK-OUT or by fan-out to CLK-IN
Custom frequencies can be supported

Acquisition Start/Stop
Daisy chain or fan-out propagation through
CLK-IN/CLK-OUT or NIM/TTL, LVDS I/Os

 

Data Sync 

Busy/Veto logic on LVDS I/Os or NIM/TTL I/Os for event building synchronization

Trigger Time Stamp

Zero from START or S-IN input
Resolution: 8 ns
Counter range: 48 bits
Full-scale range: ~625 h

Trigger Distribution

TRG-IN/TRG-OUT NIM/TTL LEMO I/Os (common trigger) or LVDS I/Os (common or individual trigger)

 

FIRMWARE

Firmware stored in the on-board Flash Memory and live rebootable by Web Interface

DPP Firmware

Implements the digital pulse processing algorithm:

  • DPP-PHA: Pulse Height Analysis
  • DPP-QDC: Charge Integration
  • DPP-PSD: Pulse Shape Discrimination
  • DPP-ZLE: Zero Length Encoding
  • DPP-DAW: Dynamic Acquisition Window
Scope Firmware

Firmware for the waveform recording

Upgrades

Any supported firmware can be uploaded via Web Interface (both different firmware types and upgraded versions of the same firmware)

 

  

 

FPGA

Xilinx Zynq UltraScale+ Multiprocessor System-on-Chip mod. XCZU19EG
Processing System based on Quad-core Arm with 2GB DDR4 memory @2400 MT/s (Linux OS onboard)
Programmable logic with more than 1100K system logic cells and 80Mbit memory

OPEN FPGA
User-Scope Template

Common trigger, simultaneous waveform recording on 64 channels management. Trigger logic and wave processing customization

User-DPP Template

Individual trigger and channel acquisition management. Customization of DPP algorithm, trigger logic, and event data information

  

COMMUNICATION INTERFACES
Optical Link (optional)

CONET, CAEN proprietary protocol

USB
Type-C connector
USB 3.0 version
Transfer rate up to 280 MB/s
1/10 Gigabit Ethernet

SFP+ receptacle for 1/10 GbE Copper (RJ-45) or Optical links (50/125µm OM2 or OM3 fiber)
TCP-IP stack implemented in the on-board Arm
Transfer rate up to 110 MB/s @1G

 

SOFTWARE
 Readout SW

  • CoMPASS spectroscopy software
    (for DPP only)
  • WaveDump2
    (for Scope firmware only)
SDK and Tools

General purpose C libraries with demo samples for host Windows® and Linux® PC, and embedded Arm processor

Web Interface

Firmware management (e,g. upgrades and on-the-fly selection of the firmware to run), board information, PLL and Ethernet configuration, board status monitoring

  

 

POWER REQUIREMENTS
+12V +5V +3.3V  
VX2745 0.9 A (Typ.) 3.6 A (Typ.) 4.4 A (Typ.)

 

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Accessories

A372F
64 channel 2.54mm Male Header Connector Adapter for x2740 Digitizers
A372M
64 channel MCX Coax Connector Adapter for SE signals
A319A
Clock & Sync cable assembly for Digitizer Series 2.0 - 20 cm
A319B
Clock cable assembly from Digitizer Series 1.0 to Digitizer Series 2.0 - 20cm

Ordering Options

Code Description
WVX2745XAAAA VX2745 - 64 Ch. 16 bit 125 MS/s Digitizer with Programmable Input Gain, Diff   RoHS
WVX2745BXAAA VX2745B - 64 Ch. 16 bit 125 MS/s Digitizer with Programmable Input Gain, SE   RoHS

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