DT2745
Coming Soon
64 Channel 16 bit 125 MS/s Digitizer with Programmable Input Gain
Features
- 16-bit @ 125 MS/s ADC
- 64 analog inputs, differential or single-ended, on four 2mm 40-pin header connectors
- Software selectable Analog Gain up to x100
- Wide range of applications (from Neutrino Physics & Dark Matter to Nuclear and Particle Physics to Spectroscopic Imaging)
- Suited for signals from Semiconductor Detectors coupled with CSPs (Si, HPGe) or scintillators coupled with PMTs (NaI, CsI)
- On-board firmware selection for different acquisition modes:
- Scope mode (simultaneous raw waveform acquisition on common trigger)
- DPP-PHA mode (pulse height and time acquisition on independent channel self-triggers)
- Predisposition for other planned algorithms: QDC, PSD, CFD, DAW, ZLE, etc.
- Multi-board synchronization and system building capabilities
- Rack mount brackets included
- Front panel fully programmable I/Os (4 LEMO TTL/NIM and 16 LVDS)
- Special 125MS/s 14bit DAC output (LEMO) for signal inspection, pulse generation, majority level
- 2.5GB of Total Acquisition memory (DDR4)
- On-board Zynq® UltraScale +™ MPSoC integrating an Arm®-based CPU running Linux®
- Multi Interface: USB-3.0 and 1/10 GbE or CONET optical link (switchable on the same socket)
- Fully supported by CoMPASS and WaveDump2 readout software (CoMPASS support is Coming Soon)
- SDK for embedded Arm and host PC
- Open FPGA architecture for pulse analysis algorithm customization
Overview
The DT2745 Digitizer is a 64-channel digital signal processor for radiation detectors in a Desktop form factor. It offers not only waveform digitization and recording but also Multi-Channel Analysis for nuclear spectroscopy using Silicon strip, segmented HPGe, Scintillation detector with PMTs, Wire Chambers, and others.
Independently for each of the 64 channels, the DT2745 can perform pulse height measurements (PHA), and other algorithms that will be gradually developed, such as constant fraction timing (CFD), charge integration (QDC) and pulse shape discrimination (PSD). The input channels with software selectable analog gain up to x100 are provided as differential (on 2745 versions) or single-ended (on 2745B versions).
Each channel of the module digitizes the analog input, that can be the signal coming from a physics detector, with a 16 bit, 125 MS/s ADC. The sampled data are used to initiate the digital pulse processing sequence, managed in the FPGA at the firmware level. Different firmware types can be selected via software, according to the specific setup and acquisition mode.
- Common trigger: all channels acquire simultaneously with a common trigger. The trigger can be fed externally or generated by a combination of individual channel discriminators. This mode is mainly intended for the acquisition of waveforms, like a digital oscilloscope. Options for zero suppression are available to remove not significant data.
- Independent trigger: suited for trigger-less applications, where no global trigger is needed but each channel acquires waveforms upon its self-trigger which fires through a digital discriminator, independently of the others.
- DPP: real-time processing in the FPGA allows for the extraction of physical parameters from the waveform (e.g. pulse height, charge, timestamp, PSD), well suited for high counting rate applications. It is yet possible to save both raw waves and parameters.
A template of the firmware is available for customers who want to personalize the acquisition to implement custom algorithms for pulse processing in the open FPGA. The user can have control of the data output information and customize the trigger logic to get several combinations of self-triggers and I/O signals to validate or discard the events.
Custom software can run on the onboard CPU for data reduction and analysis. Multi-board synchronization can be implemented via backplane or front panel easy-cabling options.
Fast readout options are available, like Ethernet 1Gb or 10Gb, USB3.0 (tested up to 280 MB/s), and optical link (CAEN Daisy Chainable Optical Link Protocol Coming Soon).
Technical Specifications
- GENERAL
Form Factor ▪ 338 W x 98 H x 290 L mm³ (including connectors)
▪ 338 W x 98 H x 280 L mm³ (without connectors)
Weight 3120 g
- ANALOG INPUT
Channels 64 channels
Differential on 2740 versions
Single-ended on 2740B versionsImpedance
50 Ω single-ended
100 Ω differentialConnector Four 2mm 40-pin header male
Input adapters availableFull Scale Range
4VppGain
x1 to x100 in steps of 0.5dB (software selectable)Bandwidth (-3 dB) 20 MHz
Offset
Individual offset adjustable in the ±1.25V range
- DIGITAL CONVERSION
Resolution 16 bits
Sampling Rate 125 MS/s (simultaneously on each input)
- SYSTEM PERFORMANCE
ENOB 12 @ 5MHz, -3dB, Gain = 1 (Typ.)
RMS 3.6 LSB (≃ 110 µV) typical RMS @ Gain = 1
- DIGITAL I/O
CLK-IN Two differential pairs:
▪ CLK: reference clock signal
▪ SYNC: synchronization signal (start/stop, T0, etc.)
AC-coupled LVDS, ECL, PECL, LVPECL, CML
Zdiff = 100 Ω
2.54mm 4-pin AMPMODU Mod II male connectorAC-coupled LVDS, ECL, PECL, LVPECL, CML
Zdiff = 100 Ω
2.54mm 4-pin AMPMODU Mod II male connectorCLK-OUT Same functionalities as CLK-IN
Daisy chainable in multi-board synchronization
LVDS
2.54mm 4-pin AMPMODU Mod II male connectorLVDS I/O
16 differential pairs
Software programmable I/O (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.)
LVDS
Zdiff = 100 Ω (when set as inputs)
2.54mm 34-pin AMPMODU Mod II male connectorTRG-IN/TRG-OUT/GPIO/S-IN General purpose I/Os
Software programmable (trigger, gate, veto, busy, etc.)
Sigle-ended TTL/NIM- TRG-IN/S-IN internally terminated with 50 Ω (Zin = 50 Ω)
- TRG-OUT requires Rt = 50 Ω
- GPIO as Input must be terminated with 50 Ω
- GPIO as TTL Output requires Rt = 50 Ω
- GPIO as NIM Output requires Rt = 50 Ω or 25 Ω
LEMO 00 male connector
- DAC OUT
DAC output for signal inspection, pulse generation, majority level
14-bit Digital-to-Analog Converter (DAC)
125MS/s Update Rate
±1 V @ 50Ω load; ±2 V @ hi-Z load Output Range
LEMO 00 male connector
- ACQUISITION MEMORY
2.5 GB total DDR4 memory size (20.971 MS/ch) divisible in multiple buffers
Maximum record length: ≃ 168 ms @ 125 MS/s (total memory size divided by 2)11 Value referred to the Scope firmware (minimum of two buffers admitted)
- TRIGGER MODES
- Common: all channels acquire simultaneously with the trigger (software, external or logic combination of self-triggers)
- Individual: each channel acquires independently with its self-trigger
- Correlated: the individual self-trigger of each channel is validated by the coincidence/anticoincidence logic between other self-triggers and/or external I/Os
- SYNCHRONIZATION
Clock Propagation Typical 62.5MHz frequency distributed by daisy chain
through CLK-IN/CLK-OUT or by fan-out to CLK-IN
Custom frequencies can be supportedAcquisition Start/Stop
Daisy chain or fan-out propagation through
CLK-IN/CLK-OUT or NIM/TTL, LVDS I/OsData Sync Busy/Veto logic on LVDS I/Os or NIM/TTL I/Os for event building synchronization
Trigger Time Stamp Zero from START or S-IN input
Resolution: 8 ns
Counter range: 48 bits
Full-scale range: ~625 hTrigger Distribution
TRG-IN/TRG-OUT NIM/TTL LEMO I/Os (common trigger) or LVDS I/Os (common or individual trigger)
- FIRMWARE
Firmware stored in the on-board Flash Memory and live rebootable by Web Interface
DPP Firmware Implements the digital pulse processing algorithm:
- DPP-PHA: Pulse Height Analysis
- DPP-QDC: Charge Integration
- DPP-PSD: Pulse Shape Discrimination
- DPP-ZLE: Zero Length Encoding
- DPP-DAW: Dynamic Acquisition Window
Scope Firmware Firmware for the waveform recording
Upgrades Any supported firmware can be uploaded via Web Interface (both different firmware types and upgraded versions of the same firmware)
- FPGA
Xilinx Zynq UltraScale+ Multiprocessor System-on-Chip mod. XCZU19EG
Processing System based on Quad-core Arm with 2GB DDR4 memory @2400 MT/s (Linux OS onboard)
Programmable logic with more than 1100K system logic cells and 80Mbit memory
- OPEN FPGA
User-Scope Template Common trigger, simultaneous waveform recording on 64 channels management. Trigger logic and wave processing customization
User-DPP Template Individual trigger and channel acquisition management. Customization of DPP algorithm, trigger logic, and event data information
- COMMUNICATION INTERFACE
Optical Link (optional) CONET, CAEN proprietary protocol
USB
Type-C connector
USB 3.0 version
Transfer rate up to 280 MB/s1/10 Gigabit Ethernet SFP+ receptacle for 1/10 GbE Copper (RJ-45) or Optical links (50/125µm OM2 or OM3 fiber)
TCP-IP stack implemented in the on-board Arm
Transfer rate up to 110 MB/s @1G
- SOFTWARE
Readout SW - CoMPASS spectroscopy software
(for DPP only) - WaveDump2
(for Scope firmware only)
SDK and Tools General purpose C libraries with demo samples for host Windows® and Linux® PC, and embedded Arm processor
Web Interface Firmware management (e,g. upgrades and on-the-fly selection of the firmware to run), board information, PLL and Ethernet configuration, board status monitoring
- CoMPASS spectroscopy software
- POWER REQUIREMENTS
Mains-powered (130 Watt @110V/220V).
Compare
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Accessories
- A372F
- 64 channel 2.54mm Male Header Connector Adapter for x2740 Digitizers
- A372M
- 64 channel MCX Coax Connector Adapter for SE signals
- A319A
- Clock & Sync cable assembly for Digitizer Series 2.0 - 20 cm
- A319B
- Clock cable assembly from Digitizer Series 1.0 to Digitizer Series 2.0 - 20cm
- DT2745
- 64 Channel 16 bit 125 MS/s Digitizer with Programmable Input Gain
Ordering Options
| Code | Description |
|---|---|
| WDT2745BXAAA | DT2745B - 64 Ch. 16 bit 125 MS/s Digitize with Programmable Input Gain, SE RoHS |
| WDT2745XAAAA | DT2745 - 64 Ch. 16 bit 125 MS/s Digitizer with Programmable Input Gain, Diff RoHS |
Related Products
Related Software
WaveDump2
Readout application for CAEN Open FPGA Digitizers