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V1724

8 Channel 14 bit 100 MS/s Digitizer

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Overview

The CAEN Mod. V1724 is a digitizer able to record waveforms along with performing advanced algorithms for online digital pulse processing (DPP) of pulse height analysis and dynamic acquisition window.

Data is read by a Flash ADC, 14-bit resolution and 100 MS/s sampling rate, which is well suited for high-resolution detectors as Silicon, HPGe or inorganic scintillators like NaI or CsI coupled with Charge Sensitive Preamplifiers. In the waveform recording mode, algorithms of zero suppression are also implemented to reduce the data throughput. The acquisition can be channel independent and it is possible to make coincidence/anti-coincidence logic among different channels and external veto/gating. Multiple boards can be synchronized to build up complex systems.

In the case of DPP mode, data can be saved in time-stamped list mode to support higher input rates and improve the throughput performances. Piled-up events can be rejected or saved for offline analysis. The acquisition in DPP-PHA mode is fully controlled by the CoMPASS and MC2Analyzer software, which manage the algorithm parameters, build the plots and saves the relevant energy and time spectra. In the case of waveform recording mode, the user can take advantage of the CAENScope and WaveDump software to access and save the waveforms. For DPP-DAW mode, a c demo fully controls the acquisition, data plotting and saving.

Libraries and demo software in C and LabView are available for integration and customization of specific acquisition systems.

The V1724 comes in a VME form factor with 8 input channels. The communication to and from the board is provided through the VMEBus and Optical Link interfaces.

Technical Specifications

GENERAL
Form Factor
1-unit wide, 6U VME64
Weight
535 g
ANALOG INPUT
Channels
8 channels single-ended

Impedance
50 Ohm

Bandwidth
40 MHz
Connector
MCX

Full-Scale Range
2.25 Vpp (default)
0.5 Vpp and 10 Vpp (on request)

Offset
Programmable DAC for DC
offset adjustment in the full range
Abs Max Rating
@2.25 Vpp: 6 Vpp (with Vrail max +6 V or –6 V for any DAC offset value)
DIGITAL CONVERSION
Resolution
14 bits
Sampling Rate
100 MS/s simultaneously on each channel
16.1 MS/s minimum by hardware down-sampling (see AN6308)
781 kS/s minimum by firmware decimation (Waveform recording firmware only)
SYSTEM PERFORMANCES
ENOB: 11.89 (64 kS Buffer)
SINAD: 73.85 dB
THD: 87.8 dB
SFDR: 93.5 dB
SIGMA: 1.09 LSB rms (64 kS buffer, open input)
ADC CLOCK GENERATION

Clock source: internal/external
Onboard programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference

DIGITAL I/O
CLK-IN (AMP Modu II)
AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by CAEN adapter)
Jitter<100 ppm requested

CLK-OUT (AMP Modu II)
DC coupled LVDS output clock for multi-board synchronization
TRG-OUT (LEMO)
Local trigger digital output
NIM/TTL, Rt = 50 Ω



TRG-IN (LEMO)
External trigger digital input
NIM/TTL, Zin = 50 Ω
S-IN (LEMO)
SYNC/START front panel digital input
NIM/TTL, Zin = 50 Ω
ACQUISITION MEMORY
  • 512 kS/ch (5 ms @ 100 MS/s) or 4 MS/ch (40 ms @ 100 MS/s) Multi Event Buffer divisible into 1 ÷ 1024 buffers
  • Independent read and write access
  • Programmable event size and pre/post-trigger
TRIGGER
Trigger Source
– Self-trigger: channel over/under threshold for either Common or Individual (DPP only) trigger generation
– External-trigger: Common by TRG-IN connector
– Software-trigger: Common by software command

Trigger Propagation
TRG-OUT digital output
Trigger Time Stamp
– Waveform Recording: 31-bit counter, 20 ns resolution, 21 s range; 48-bit extension by firmware
– DPP-PHA: 30-bit counter, 10 ns resolution, 64-bit extension by software
– DPP-DAW: 31-bit counter, 10 ns resolution, 21 s range; 64-bit extension by software
SYNCHRONIZATION
Clock Propagation
Daisy chain: CLK-IN/CLK-OUT connectors
One-to-many: clock distribution from DT4700 on CLK-IN connector
Clock Cable delay compensation
Acquisition Synchronization
Sync Start/Stop through digital I/O (S-IN or TRG-IN input, TRG-OUT output)
Trigger Time Stamp Alignment
By S-IN input connector
ADC & MEMORY CONTROLLER FPGA

One Altera Cyclone EP1C20 per channel

ANALOG MONITOR

12 bit / 100 MHz DAC FPGA controlled output with five operating modes:

  • Test Waveform: 1 Vpp test ramp generator
  • Majority signal: proportional to the number of channels (enabled) under/over threshold (steps of 125 mV)
  • Inspection signal: proportional to the sum of the board channels
  • Memory Occupancy signal: proportional to the Multi-Event Buffer Occupancy (1 buffer ~ 1 mV)
  • Voltage level: programmable output voltage level
LVDS I/O
  • 16 general-purpose LVDS I/Os controlled by FPGA
  • Busy, Data Ready, Memory Full, Individual Trg-Out and other functions can be programmed
  • An Input Pattern from the LVDS I/Os can be associated to each trigger as an event marker
COMMUNICATION INTERFACE
VME
VME 64X compliant
Data transfer mode: BLT32, MBLT64 (70 MB/s using CAEN Bridge), CBLT32/64, 2eVME, 2eSST (up to 200 MB/s)
Optical Link
CAEN CONET proprietary protocol, up to 80 MB/s transfer rate
Daisy chainable: it is possible to connect up to 8 ADC modules to a single Optical Link Controller (Mod.A2818/A3818/A4818)
FIRMWARE
Waveform Recording Firmware
Free firmware for waveform recording

Upgrades
Firmware can be upgraded via Optical Link or VMEBus
DPP Firmware
Paid firmware for Digital Pulse Processing: DPP-PHA, and DPP-DAW
SOFTWARE

Libraries: General-purpose C and LabVIEW Libraries
Configuration Tools: CAEN Upgrader for Firmware upgrade, Direct Register, Example codes
Readout Software: CAEN WaveDump, CAENScope, CoMPASS, MC2Analyzer, DPP-DAW Demo software

VENTILATION REQUIREMENTS

V1724 cannot be operated with CAEN crates VME8001/8002/8004/8004A (weak cooling air flow).

POWER CONSUMPTIONS

4.5 A @ +5 V
200 mA @ +12 V
200 mA @ -12 V

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Accessories

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Optical Fiber Series
A654
Cable assembly LEMO 00 male to MCX male – 1 m
A659
Cable assembly BNC male to MCX male – 1 m
A317
Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm
A318
Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
A316
Cable assembly 2.54mm 2-pin header female - 5 cm
A952
Cable assembly 2.54mm 34 pin female to 2.54mm 34 pin female - 50 cm
A953
Cable assembly 2.54mm 34 pin female to two 2.54mm 34 pin female – 50 cm
A954
Cable assembly 2.54mm 34 pin female to two 2.54mm 16 pin female - 50 cm
A4818
USB 3.0 to CONET2 Adapter
Digitizers Input Range Personalizations
Digitizers Input Range Customizations

Ordering Options

Code Description
WV1724BXAAAA V1724B - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, SE  (Obsolete)
WV1724CXAAAA V1724C - 8 Ch. 14 bit 100 MS/s Digitizer: 512KS/ch, C4, DIFF  (Obsolete)
WV1724DXAAAA V1724D - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, DIFF  (Obsolete)
WV1724EXAAAA V1724E - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, SE   RoHS
WV1724FXAAAA V1724F - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, DIFF  (Obsolete)
WV1724GXAAAA V1724G - 8 Ch. 14 bit 100 MS/s Digitizer: 512KS/ch, C20, SE   RoHS
WV1724XAAAAA V1724 - 8 Ch. 14 bit 100 MS/s Digitizer: 512KS/ch, C4, SE  (Obsolete)

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