VX1742
32+2 Channel 12bit 5 GS/s Digitizer
Features
- 12 bit @ 5 GS/s, 1-unit wide 6U VME64 module
- Switched Capacitor technology based on the DRS4 chip (designed at Paul Scherrer Institute)
- 1024 capacitor cells per channel (acquisition window of ~ 200 ns @ 5 GS/s)
- 5 GS/s, 2.5 GS/s, 1 GS/s, 750 MS/s software selectable sampling frequencies
- 32 analog input channels on MCX coaxial connectors
- 2 additional analog inputs (TR0 and TR1):
- fast (low latency) trigger
- digitizable for high resolution timing (up to 50 ps)
- 1 Vpp input dynamic range (2 Vpp on request) with programmable DC offset adjustment
- Dead-time due to conversion: 110 µs (analog inputs only), 181 µs (TR0, TR1 inputs)
- Trigger modes:
- External on TRG-IN connector; common to all groups
- Fast (Low Latency) on TR0 and TR1 connectors; common to couples of groups
- Self-trigger, combinations of channels over-threshold in logic OR; common to couples of groups
- Memory buffer options: 128 events/ch; 1024 events/ch
- VME64 (VME64X compliant) and Optical Link communication interfaces
- Multi-board synchronization features
- 16 programmable LVDS I/Os
- Demo software tools, C and LabVIEW libraries
Overview
The Mod. VX1742 is a 1-unit wide VME64X board housing 32+2 Channel 12 bit 5 GS/s Switched Capacitor Digitizer sections. The input dynamic range is 1 Vpp on single-ended MCX coaxial connectors (16-bit DAC on each channel to control the DC Offset).
The digitizer is based on the Switched Capacitor Array DRS4 chip (Domino Ring Sampler). This technology relies on a series of 1024 capacitors (analog memory) in which the analog input signal is continuously sampled in a circular way.
The sampling frequency is 5 GHz by default and it can be programmed to 2.5 GHz, 1GHz, and 750 MHz. The analog to digital conversion is not simultaneous with the chip sampling phase, and it starts as soon as the trigger condition is met, thus producing a dead time of 110 μs in case only the analog inputs are digitized, 181 μs when also the fast trigger TRn is digitized. When the trigger stops the DRS4 chip sampling (holding phase), the analog memory buffer is frozen, and the cell content is made available to the 12 bit ADC for the digital conversion.
The digital memory allows to store subsequent events, even if the readout is not yet started. Moreover, since the digital memory buffers work like FIFOs, the readout activity from VME or Optical Link does not affect write operations of subsequent events.
The available trigger sources are:
- External Trigger, trigger on TRG-IN connector, common to all enabled groups.
- Fast (Low Latency) Local Trigger, trigger on TR0 and TR1 connectors, common to couples of groups. This mode is called “Fast” or “Low Latency” since the trigger latency to hold the DRS4 is reduced with respect to the external trigger. This trigger mode is convenient for high precision timing measurements, since the TRn can be digitized and reported in the output data to be used as time reference.
- Self-trigger, common to couples of groups. For each group is possible to select combination of channels (logic OR) that provide a trigger whenever the input crosses the threshold. This mode cannot be used at 5 GHz due to the trigger latency.
The module features the front panel CLK IN/CLK OUT connectors and an internal PLL for clock synthesis from internal/external references. V1742 supports multi-board synchronization allowing all DRS4s to be synchronized with a common clock source and ensuring Trigger Time Stamps alignment. Once synchronized, all data will be aligned and coherent across multiple V1742 boards.
The module is available with digital memory sizes of 128 event/ch or 1024 event/ch.
The VME interface of the module is VME64X compliant, and the data readout can be performed in several data transfer modes: BLT32, MBLT64 (up to 70 MB/s of transfer rate using CAEN Bridge), CBLT32/64, 2eVME, 2eSST (up to 200 MB/s of transfer rate). The built-in daisy chainable Optical Link is able to transfer data at 80 MB/s, thus it is possible to connect up to 8 boards to a single A2818 Controller, or up to 32 to a single A3818 Controller (4-link version).
Software available (Windows and Linux): CAEN provides drivers for all the different types of physical communication channels, a set of C and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:
- CAENUpgrader: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.
Software for V1742 running Waveform Recording Firmware:
- CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.
Technical Specifications
- Mechan
Form Factor: 1‐unit wide VME64/VME64X boards
Weight: 520 g
Dimension: 6U x 160 mm
- Analog Input
Channels - 32 channels
- 2 special channel (TR0, TR1)
- Single ended
Full Scale Range (FSR)
- 1 Vpp
Absolute max analog input voltage
- 3Vpp (with Vrail max +3V or ‐3V) for any DAC offset in single ended configuration
Impedance
Zin = 50 OhmDC Offset
- Programmable 16-bit DAC for DC offset adjustment on each channel. Range ± 1 V
Connector
MCXBandwidth
500 Mhz
- Digital Conversion
Resolution - 12 bits
Switched Capacitor
- Array Domino Ring Sampler chip (DRS4), 8+1 channels with 1024 storage cells each
Sampling Rate - 5 GS/s – 2.5 GS/s – 1 GS/s – 0.75 GS/s SW selectable, simultaneously on each channel
Dead Time (A/D Conversion) - 110 μs, analog inputs only 181 μs, digitizing TR0
- FPGA
Altera Cyclone EP3C16 (one FPGA manages 16+1 channels)
- Trigger
Trigger Source
‐ Fast (Low Latency) trigger: Programmable threshold on TR0 and TR1 (each TRn signal drives two 8‐ch groups)
‐ Self‐trigger: Logic OR combination of channels over/under threshold (each channel self‐trigger drives two 8‐ch groups)
‐ External‐trigger: Common trigger by TRG‐IN connector
‐ Software‐trigger: Common trigger by software commandTrigger Propagation
TRG‐OUT programmable
digital outputTrigger Time Stamp
30‐bit counter (extendable to 60‐bit by sw)
8.5 ns resolution
9 s range
Timer reset by S‐IN
- Acquisition Memory
128 events/ch (1024 S/event; 26 us @ 5 GS/s) or 1024 events/ch (1024 S/event; 209 us @ GS/s) Multi‐event buffers
Independent read and write access
Programmable event size and pre/post‐trigger
- ADC Clock Generation
Clock source: internal/external.
On‐board programmable PLL provides generation of the main board clocks from internal
(50 MHz local Oscillator) or external (front panel CLK‐IN connector) reference
- Digital I/O
CLK-IN (AMP Modu II) AC coupled differential input clock
LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by A318 adapter) Jitter < 100 ppm requestedCLK-OUT (AMP Modu II)
DC coupled differential
LVDS clock output locked at ADC sampling clockTRG-IN (LEMO) External trigger digital input
NIM/TTL
Zin = 50 OhmTRG-IN (LEMO)
Trigger digital output
NIM/TTL
Zin = 50 OhmS‐IN (LEMO)
SYNC/START
front panel digital input
NIM/TTL
Signal Width > 17 ns
Zin = 50 ΩLVDS I/O
16 general purpose LVDS
I/O controlled by the FPGA:
Busy, Data Ready, Memory full, Individual Trig‐Out and other functions can be programmed.
An Input Pattern from the LVDS I/O can be associated to each trigger as an event marker
- Synchronization
Clock Propagation
- Daisy chain: through CLK‐IN/CLK‐OUT connectors
- One‐to‐many: clock distribution from an external clock source to CLK‐IN connector
- Clock Cable delay compensation
Acquisition Synchronization
- Sync, Start/Stop through digital I/Os (S‐IN or TRG‐IN input / TRG‐OUT output)
Trigger Time Stamps Alignment
- By S‐IN input connector
- Data Alignment
- Busy/Veto management through digital
- I/Os (TRG‐OUT/TRG‐IN) or LVDS I/Os
- Communication Interfaces
Optical Link: CAEN CONET proprietary protocol, Up to 80 MB/s transfer rate, Daisy‐chain capability.
VME: VME 64X compliant. Data transfer mode: BLT32, MBLT64 (70 MB/s by CAEN Bridge), CBLT32/64, 2eVME, 2eSST (200 MB/s).
- Firmware
Waveform Recording Firmware
Free firmware for waveform recordingUpgrades
Supported via VMEbus/Optical Link
- Software
Readout SW
WaveDump readout software with C source files and VS project for developers (Windows® , Linux®)Libraries and Tools
General purpose C libraries with readout demos (Windows® , Linux® , and LabVIEW™ support) and configuration tools
- Environmental
Environment: Indoor use
Operating Temperature: 0◦C to +40◦C
Storage Temperature: –10◦C to +60◦C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity: 5% to 90% RH non condensing
Altitude: < 2000m
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: IPX0 Enclosure, not for wet location
- Regulatory Compliance
EMC: CE 2014/30/EU Electromagnetic compatibility Directive
Safety: CE 2014/35/EU Low Voltage Directive
- Power Requirements
5.5 A @ +5V
200 mA @ +12V
300 mA @ ‐12V

- Documentation
- Software
- Firmware
Free
Data Sheet
Manuals
Guides
Brochures, Flyers
Application Notes
White Papers
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Accessories
- A4818
- USB 3.0 to CONET2 Adapter
- A316
- Cable assembly 2.54mm 2-pin header female - 5 cm
- A317
- Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm
- A318
- Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
- DT4700
- Clock Generator and FAN-OUT
- A654
- Cable assembly LEMO 00 male to MCX male – 1 m
- A659
- Cable assembly BNC male to MCX male – 1 m
- A952
- Cable assembly 2.54mm 34 pin female to 2.54mm 34 pin female - 50 cm
- A953
- Cable assembly 2.54mm 34 pin female to two 2.54mm 34 pin female – 50 cm
- A954
- Cable assembly 2.54mm 34 pin female to two 2.54mm 16 pin female - 50 cm
- AI2700
- Optical Fiber Series
- Digitizers Input Range Personalizations
- Digitizers Input Range Customizations
Ordering Options
Code | Description |
---|---|
WVX1742BXAAA | VX1742B - 32+2 Ch. 12 bit 5GS/s Switched-CapacitorDigitizer: 1024 events/ch (1kS/event), EP3C16, SE RoHS |
WVX1742XAAAA | VX1742 - 32+2 Ch. 12 bit 5GS/s Switched-CapacitorDigitizer: 128 events/ch (1kS/event), EP3C16, SE RoHS |