DT5730 / DT5730S
8 Channel 14 bit 500 MS/s Digitizer
Features
- 14-bit @ 500 MS/s
- Analog inputs on MCX coaxial connectors
- NSCLDAQ Supported (DPP-PSD and DPP-PHA only)
- 8 channels, Desktop module
- 0.5 and 2 Vpp selectable input dynamic range with programmable DC offset adjustment
- Algorithms for Digital Pulse Processing (Free Trial)
- USB and Optical Link communication interfaces
- Multi-board synchronization features
- Daisy chain capability
- Compliant with CoMPASS, MC2Analyzer, DPP-ZLEplus and DPP-DAW Demo Software, C and LabVIEW libraries
Overview
The CAEN Mod. DT5730S is a digitizer capable of recording waveforms along with performing advanced algorithms for online digital pulse processing (DPP) (Free Trial). Utilizing DPP Firmware, users can acquire quantitative physical parameters (Integrated Charge, Pulse Shape Discrimination with very fine time resolution, Pulse Height Analysis) as well as read out waveforms with automatic pulse identification and baseline suppression on channel basis (Zero-Length Encoding and Dynamic Acquisition Window). The wide range of DPP algorithms supported by the DT5730S make it a “must-have” for any type of nuclear physics application.
The DT5730S (previously DT5730) has also been upgraded, introducing a larger FPGA to accommodate more complex DPP algorithms and a new A/D converter for better stability which does not require temperature-related calibration.
Input signals are read by a Flash ADC, 14-bit resolution and 500 MS/s sampling rate, which is well suited for mid fast signals as the ones coming from liquid or inorganic scintillators coupled to PMTs or Silicon Photomultipliers, but also for high precision detectors as Silicon or HPGe coupled with charged sensitive preamplifier. The acquisition can be channel independent and it is possible to make coincidence/anti-coincidence logic among different channels and external veto/gating. Multiple boards can be synchronized to build up complex systems. In the case of DPP mode, data can be saved in time-stamped list mode to support higher input rates and improving the throughput performances. Piled-up events can be rejected or saved for offline analysis. The acquisition in DPP mode is fully controlled by the CoMPASS and MC2Analyzer software, which manage the algorithm parameters, build the plots and saves the relevant energy, time, and PSD spectra. In the case of waveform recording mode, the user can take advantage of the CAENScope and WaveDump software to access and save the waveforms. Libraries and demo software in C and LabView are available for integration and customization of specific acquisition systems.
The DT5730S comes in a Desktop form factor, with 8 input channels. The communication to and from the board is provided through the USB and Optical Link interfaces.
Technical Specifications
- GENERAL
Form Factor: 154x50x164 mm3 (WxHxD) Desktop
Weight: 670 g
- ANALOG INPUT
Channels: 8 channels single ended
Impedance: 50 Ω
Connector: MCX
Full-Scale Range: 0.5 or 2 Vpp (SW selectable)
Bandwidth: 250 MHz
Offset: Programmable DAC for DC offset adjustment in the full-scale range
- DIGITAL CONVERSION
Resolution: 14 bits
Sampling Rate: 500 MS/s Simultaneously on each channel
- SYSTEM PERFORMANCES
DT5730Sx Baseline RMS Noise (open inputs)
@ 2 Vpp: 2.6 LSB = 312 uV
@ 0.5 Vpp: 3.4 LSB = 102 uV
- ADC CLOCK GENERATION
- Clock source: internal/external
- Onboard programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference
- DIGITAL I/O
- CLK-IN (AMP Modu II)
AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by CAEN adapter)
Jitter < 100 ppm requestedGPO (LEMO)
General purpose digital output
NIM/TTL, Rt = 50 Ω
GPI (LEMO)
General purpose digital input
NIM/TTL, Zin = 50 ΩTRG-IN (LEMO)
External trigger digital input
NIM/TTL, Zin = 50 Ω
- ACQUISITION MEMORY
- 640 kS/ch (1.25 ms @ 500 MS/s) or 5.12 MS/ch (10 ms @ 500 MS/s) Multi-event Buffer divisible into 1 ÷ 1024 buffers
- Independent read and write access
- Programmable event size and pre/post-trigger
- TRIGGER
- Trigger Source
Self-trigger: channel over/under threshold for either Common or Individual (DPP only) trigger generation
External-trigger: Common by TRG-IN connector
Software-trigger: Common by software command
Trigger Propagation
GPO digital outputTrigger Time Stamp
Waveform Recording: 31-bit counter, 16 ns resolution, 17 s range; 48-bit extension by firmware
DPP-PSD: 47-bit counter, 2 ns resolution, 78 h range; 10-bit and 2 ps fine time stamp with digital CFD
DPP-PHA: 47-bit counter, 2 ns resolution, 78 h range
DPP-DAW: 48-bit counter, 2 ns resolution, 156 h range
DPP-ZLEplus: 48-bit counter, 16 ns resolution, 625 h range
- SYNCHRONIZATION
- Clock Propagation
One-to-many: clock distribution from DT4700 to CLK-IN connectorAcquisition Synchronization
Sync Start/Stop through digital I/O (TRG-IN input, GPO output)Trigger Time Stamp Alignment
By GPI input connector
- ADC & MEMORY CONTROLLER FPGA
- DT5730
Altera Cyclone EP4CE30
(one FPGA serves 4 channels)DT5730S
Intel/Altera Arria V GX
(one FPGA serves 4 channels)
- COMMUNICATION INTERFACE
- USB
USB 2.0 compliant
Transfer rate up to 30 MB/s
- FIRMWARE
- Waveform Recording Firmware
Free firmware for waveform recording
Upgrades
Firmware can be upgraded via Optical Link or USB
- POWER REQUIREMENTS* (typ. @+12 VDC)
Firmware DT5730 DT5730B DT5730S DT5730SB Wav. Rec. 2.8 A 3.0 A 2.9 A 3.5 A DPP-PHA N.A.** 2.9 A 3.4 A DPP-PSD 2.9 A 3.2 A DPP-DAW 2.9 A 3.4 A DPP-ZLE 2.3 A 3.2 A * The declared values are measured in standard operating conditions. In general, they could be subject to slight change due to the firmware type, the firmware version, and the operating mode.
** Not measured values can be assumed to respect the same proportions as the relevant “S” model ones.
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Accessories
- A654
- Cable assembly LEMO 00 male to MCX male – 1 m
- A659
- Cable assembly BNC male to MCX male – 1 m
- AI2700
- Optical Fiber Series
- A318
- Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
- A317
- Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm
Ordering Options
Code | Description |
---|---|
WDT5730BXAAA | DT5730B - 8 Ch. 14 bit 500 MS/s Digitizer: 5.12MS/ch, CE30, SE (Obsolete) RoHS |
WDT5730XAAAA | DT5730 - 8 Ch. 14 bit 500 MS/s Digitizer: 640kS/ch, CE30, SE (Obsolete) RoHS |
WDT5730SBXAA | DT5730SB - 8 Ch. 14 bit 500 MS/s Digitizer: 5.12MS/ch, Arria V GX, SE RoHS |
WDT5730SXAAA | DT5730S - 8 Ch. 14 bit 500 MS/s Digitizer: 640kS/ch, Arria V GX, SE RoHS |