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V2730B

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16 Channel 14 bit 500 MS/s Digitizer with programmable Input Gain

Features

  • 16 independent channels, 500 MS/s 14-bit, individual DC offset adjustment and Software selectable analog gain (VGA).
  • Front panel readout via USB-3.0 or 1/10Gb Ethernet
  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
  • 5GB of total acquisition memory (DDR4)
  • Open FPGA architecture fully supported by Sci-Compiler tool
  • Ready-to-Use Firmware solutions to get time-stamped waveforms and physical quantities (check here the available options).
  • Triggered and Streaming Readout modes supported
  • System features: Multi-board synchronization, digital I/Os for trigger logic, on-board storage of multiple firmware images, 125MS/s 14-bit DAC output and integrated web interface
  • Software ecosystem:
    • GUI-based readout software available for multiparametric spectroscopy (CoMPASS) or waveform recording (WaveDump2)
    • Firmware/software generator and compiler for the Open FPGA (Sci-Compiler), eliminating the need for FPGA programming skills.
    • Libraries (FELib) and demo codes are provided for software customization
  • Wide range of applications (from Nuclear and Particle Physics to High Timing Resolution, Fast Neutron Spectroscopy, and Homeland Security)
  • Suited for signals from liquid or inorganic scintillators coupled to PMTs or SiPMs.
  • Fully complianti with with CAEN μ-crate module
3 Years Warranty
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3 Years Warranty
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Overview

The V2730B Digitizer is a 16-channel digital signal processor for radiation detectors in the VME64 form factor. It offers not only waveform digitization and recording but also Multi-Channel Analysis for a complete range of applications like nuclear and particle physics, high-timing resolution, Fast Neutron Spectroscopy, and Homeland Security. It is compliant with mid-fast signals typically coming from liquid or inorganic scintillators coupled to PMTs or SiPMs.

V2730B features 16 single-ended channels, capable of digitizing detector signals using a 14-bit ADC at 500 MS/s. Data acquisition is driven by trigger signal generation and the identification of a Region of Interest (ROI), defined in terms of sample count or time duration. Trigger sources can be local (channel self-trigger), external, or software-based. Once acquired, the digitized data is processed within the FPGA, stored in high-speed memory as events—including Trigger ID and Timestamp tags—and then transferred via high-bandwidth communication interfaces for further analysis. The digitizer supports different acquisition modes, designed to balance throughput, latency, and data efficiency according to experimental requirements:

  • Triggered Mode: All channels acquire data simultaneously upon a global trigger generated by a Central Logic Unit, which processes local triggers from individual channels. External and software triggers can also be configured as sources for the global trigger. Zero suppression algorithms can be applied to remove non-significant data and reduce the readout payload.
  • Streaming Readout Mode: Each channel autonomously identifies its ROI using the self-trigger mechanism, acquiring data independently of the other channels. This mode includes automatic zero suppression (non-triggered channels are not acquired), maximizes acquisition rates, and is ideal for applications requiring real-time parameter extraction. In addition, correlation logics can be configured to validate event acquisition upon coincidences or anticoincidences between local and external triggers.

V2730B can operate using both pre-configured firmware developed by CAEN and custom user-generated firmware, offering flexibility for a wide range of applications. Multiple firmware images can be stored simultaneously in the digitizer’s FLASH memory and quickly activated when needed. CAEN provides ready-to-use firmware solutions optimized for specific acquisition and processing needs:

  • Scope Firmware: Based on full waveform recording in triggered acquisition mode. A zero suppression function is available to reduce unnecessary data readout.
  • DPP-PSD Firmware: Implements Digital Pulse Processing algorithms for charge integration and pulse shape discrimination. Physical parameters such as pulse height, charge, timestamp, and PSD are extracted from waveforms acquired in streaming readout It is yet possible to save both raw waves and parameters.
  • For users requiring custom acquisition and processing, the Open FPGA architecture enables firmware customization through Sci-Compiler. This graphical tool allows users to create personalized firmware solutions without HDL skills. In addition, Sci-Compiler automatically generates drivers and libraries and provides graphical utilities for developing custom DAQ software.

The Linux-based Arm processor embedded in the onboard CPU makes it possible to run automated user routines. Multi-board synchronization can be implemented via backplane or front panel easy-cabling options. Multiple communication interfaces offer flexible readout options: USB 3.0 type-C and 1/10 Gigabit Ethernet.

For detailed information on available firmware for the 2730 family and the structure of programming files (.CUP), please refer to the following page.

The V2730B fits in the single-slot CAEN VME64X u-crate, which allows you to convert the VME digitizer into a desktop board for lab tests. Moreover, you can check this FAQ to see which CAEN VME crates are suitable for this product.

This product is compatible with the following third-party software:

Technical Specifications

GENERAL

Weight: 700 g
Form Factor: 1-unit wide, 6U VME64
Dimension: 6U x 160 mm

ANALOG INPUT

Channels: 16 channels, single-ended
Bandwidth (-3dB): 250 MHz guaranteed for Gain ≥ 2
Impedance: 50 Ω
Gain: x1 ÷ x20, software programmable in steps of 1dB independently on each channel
Connector Type: MCX
Full Scale Range: 4 Vpp ÷ 0.2 Vpp
DC Offset: Adjustable in the ± 2.5V range independently on each channel

DIGITAL CONVERSION

Resolution: 14 bits
Sampling Rate: 500 MS/s (simultaneously on each channel)

SYSTEM PERFORMANCE

ENOB (Typ.): 10.5 (@50MHz, -3dB, Gain x2)
RMS (Typ.): 2.4 LSB RMS (@Gain x2)

DIGITAL I/O
CLK-IN (CLK-OUT)

  • Two differential pairs:
    • CLK, reference clock signal
    • SYNC, synchronization signal (start/stop, T0, etc.)
  • 2.54mm 4-pin AMPMODU Mod II male connector
  • CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)
  • CLK-OUT: LVDS
  • Daisy chainable for multiboard synchronization with sw programmable CLK-OUT delay shift
LVDS I/O

  • 16 differential pairs
  • Sw programmable I/O function (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.)
  • LVDS
  • Zdiff = 100 Ω (when set as inputs)
  • 2.54mm 34-pin AMPMODU Mod II male connector
TRG-IN/TRG-OUT/GPIO/S-IN

  • General-purpose digital I/Os
  • Sigle-ended TTL/NIM
  • LEMO 00 male connector
  • Sw programmable function (trigger, veto, busy, etc.)
  • TRG-IN/S-IN: internally terminated with 50 Ω (Zin = 50 Ω)
  • TRG-OUT requires Rt = 50 Ω
  • GPIO as Input must be terminated with 50 Ω
  • GPIO as TTL Output requires Rt = 50 Ω
  • GPIO as NIM Output requires Rt = 50 Ω or 25 Ω
ANALOG OUTPUT
  • Sw programmable DAC output for signal inspection, pulse generation, majority level
  • 14-bit Digital-to-Analog Converter (DAC)
  • 125 MS/s Update Rate
  • LEMO 00 connector
  • ±1 V @ 50Ω load
  • ±2 V @ hi-Z load Output Range
ACQUISITION MEMORY
  • 5 GB total DDR4 memory size (83.886 MS/ch) divisible in multiple buffers
  • Maximum record length: 84 ms @ 500 MS/s (total memory size divided by 2)1

(1) Value referred to the Scope firmware (minimum of two buffers admitted)

COMMUNICATION INTERFACES
1 GbE

  • Copper RJ45 or optical LC connector on SFP+ transceiver
  • TCP/IP protocol
  • Transfer rate: 110 MB/s
10 GbE (Contact CAEN Support)

  • Copper RJ45 or LC optical connector on SFP+ transceiver
  • UDP protocol
  • Transfer rate: 850 MB/s
USB 3.0

  • USB-C type connector
  • USB 3.1 GEN1 protocol
  • Transfer rate: 280 MB/s
Acquisition Modes

Triggered: All channels fire simultaneously upon a global trigger generated by the Central Trigger Logic receiving the local trigger sources: Local (self-trigger), External, Software

Streaming readout: Each channel autonomously identifies the ROI. The channel’ self-trigger is used to start the acquisition and capture events independently of the other channels. Additionally, a correlated streaming mode validates events via coincidence/anticoincidence with local or external triggers

Trigger Sources

Software: By register writing

External: Upon the leading edge of TRG-IN signal (TTL/NIM)

Local (self-trigger): Upon the channel discriminator with programmable threshold

Trigger Time Stamp
Scope Firmware DPP firmware
Resolution 8 ns coarse time stamp 2 ns coarse timestamp / 2 ps fine time stamp
Counter range 48 bits 48 bits
Full-scale range ~625 h 156 h
SYNCHRONIZATION
Clock Propagation

Typical 62.5MHz frequency optionally distributed:
• By fan-out to CLK-IN
• By CLK-IN/CLK-OUT daisy chain with sw programmable CLK-OUT delay shift
Custom frequencies can be supported on request

Acquisition Start/Stop

Daisy chain or fan-out propagation through CLK-IN/CLK-OUT or NIM/TTL, LVDS I/Os

Data Sync

Busy/Veto logic on LVDS I/Os or NIM/TTL I/Os for event building synchronization

Trigger Distribution

TRG-IN/TRG-OUT NIM/TTL LEMO I/Os (common trigger) or LVDS I/Os (common or individual trigger)

Trigger Time Stamp Reset

Software from START run command or Hardware from S-IN/GPIO input (Scope Firmware only)

FPGA
  • Xilinx Zynq UltraScale+ Multiprocessor System-on-Chip mod. XCZU19EG
  • Processing System based on Quad-core Arm with 2GB DDR4 memory @2400 MT/s (Linux OS onboard)
  • Programmable logic with more than 1100K system logic cells and 80 Mbit memory
CAEN FIRMWARE

Developed by CAEN, stored in the on-board FLASH memory, and live rebootable by Web Interface

DPP Firmware

Firmware implementing Digital Pulse Processing algorithms:

  • DPP-PSD: Pulse Shape Discrimination
  • DPP-PHA: Pulse Height Analysis (Coming Soon) 
Scope Firmware

Firmware for the waveform recording

Upgrades

CAEN firmware can be uploaded via Web Interface (scope and DPP firmware, and their updates)

USER FIRMWARE (OPEN FPGA)

Sci-Compiler
User Firmware Generator and Compiler Graphical Tool for CAEN Programmable Boards.

Scope Personalization

Customizable features of the Scope firmware:

  • Common trigger
  • Simultaneous waveform recording on 16 channels management
  • Trigger logic
  • Wave processing
DPP Personalization

Customizable features of the DPP firmware:

  • Individual trigger and channel acquisition management
  • DPP algorithm
  • Trigger logic
  • Event data information
SOFTWARE

Readout SW: CoMPASS spectroscopy software (for DPP firmware only), WaveDump2 (for Scope firmware only)

SDK and Tools: General purpose C libraries with demo samples for host Windows® and Linux® PC, and embedded Arm processor

SCI-Compiler (Open FPGA): Automatic generation of drivers (USB, ethernet), libraries, and demo software for Windows®, Linux®

Web Interface: Firmware management (e,g. upgrades and on-the-fly selection of the firmware to run), board information, PLL and Ethernet configuration, board status monitoring

ENVIRONMENTAL

Environment: Indoor use
Operating Temperature: 0°C to +40°C
Storage Temperature: -10°C to +60 °C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity 5% to 90% RH non condensing
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial

REGULATORY COMPLIANCE

EMC: CE 2014/30/EU Electromagnetic Compatibility
Directive Safety: CE 2014/35/EU Low Voltage Directive

POWER REQUIREMENTS

+12V: 0.5 A (Typ.)
+5V: 4.8 A (Typ.)
+3.3V: 8.9 A (Typ.)

These are preliminary values, referred to a 1-GbE Scope firmware, that could vary depending on the firmware type.

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Ordering Options

Code Description
WV2730BXAAAA V2730B - 16 Ch. 14 bit 500MS/s Digitizer with Programmable Input Gain   RoHS

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