DT2730
32 Channel 14 bit 500 MS/s Digitizer
Features
- 14-bit @ 125 MS/s ADC
- 32 analog inputs, differential or single-ended, on four 2mm 40-pin header connectors
- Fully supported by CoMPASS and WaveDump2 readout software
- Open FPGA programming through graphical tool SCI-Compiler
- Wide range of applications (from Neutrino Physics & Dark Matter to Nuclear and Particle Physics to Spectroscopic Imaging)
- Suited for signals from Semiconductor Detectors coupled with CSPs (Si, HPGe) or scintillators coupled with PMTs (NaI, CsI)
- On-board firmware selection for different acquisition modes:
- Scope mode (simultaneous raw waveform acquisition on common trigger)
- DPP-PHA mode (pulse height and time acquisition on independent channel self-triggers)
- DPP-PSD mode (pulse shape discrimination and time acquisition on independent channel self-triggers)
- Predisposition for other algorithms like zero suppression and data reduction
- Multi-board synchronization and system building capabilities
- Rack mount brackets included
- Front panel fully programmable I/Os (4 LEMO TTL/NIM and 16 LVDS)
- Special 125 MS/s 14bit DAC output (LEMO) for signal inspection, pulse generation, majority level
- 2.5 GB of Total Acquisition memory (DDR4)
- On-board Zynq® UltraScale +™ MPSoC integrating an Arm®-based CPU running Linux®
- Multi Interface: USB-3.0 and 1/10 GbE or CONET Coming Soon optical link (switchable on the same socket)
- SDK for embedded Arm and host PC
Overview
The CAEN Mod.DT2730 Digitizer is a 32-channel digital signal processor for radiation detectors in a Desktop form factor. It offers not only waveform digitization and recording but also Multi-Channel Analysis for nuclear spectroscopy using Silicon strip, segmented HPGe, Scintillation detector with PMTs, Wire Chambers, and others.
The DT2730 can perform pulse height measurements (PHA), and other algorithms that will be gradually developed, such as constant fraction timing (CFD), charge integration (QDC) and pulse shape discrimination (PSD). Algorithm settings can be set independently channel by channel.
Each channel of the module digitizes the analog input, that can be the signal coming from a physics detector, with a 16 bit, 125 MS/s ADC. The sampled data are used to initiate the digital pulse processing sequence, managed in the FPGA at the firmware level. Different firmware types can be selected via software, according to the specific setup and acquisition mode.
- Common trigger: all channels acquire simultaneously with a common trigger. The trigger can be fed externally or generated by a combination of individual channel discriminators. This mode is mainly intended for the acquisition of waveforms, like a digital oscilloscope. Options for zero suppression are available to remove not significant data.
- Independent trigger: suited for trigger-less applications, where no global trigger is needed but each channel acquires waveforms upon its self-trigger which fires through a digital discriminator, independently of the others.
- DPP: real-time processing in the FPGA allows for the extraction of physical parameters from the waveform (e.g. pulse height, charge, timestamp, PSD), well suited for high counting rate applications. It is yet possible to save both raw waves and parameters.
A template of the firmware is available for customers who want to personalize the acquisition to implement custom algorithms for pulse processing in the open FPGA. The user can have control of the data output information and customize the trigger logic to get several combinations of self-triggers and I/O signals to validate or discard the events.
Custom software can run on the onboard CPU for data reduction and analysis. Multi-board synchronization can be implemented via backplane or front panel easy-cabling options.
The communication interface selection offers fast readout options: USB 3.0 type-C and 1/10 Gigabit Ethernet or optional Optical (CONET – CAEN Daisy Chainable Optical Link Protocol Coming Soon) Links.
Technical Specifications
- GENERAL
Weight: 3120 g
Form Factor: Desktop | Desktop Rack
Dimension: Desktop: 338 W x 100 H x 283 L mm³ (without connectors) | 338 W x 100 H x 295 L mm³ (including connectors). Desktop-Rack: 19” rack mount
- POWER REQUIREMENTS
Mains-powered (130 Watt @110V/220V).
- ANALOG INPUT
Channels 32 channels Single-Ended
Impedance
50 ΩConnector MCX
Full Scale Range
4 Vpp ÷ 0.2 VppBandwidth (-3 dB) 250 MHz
Offset
Individual offset adjustable in the ±2.5V range
- DIGITAL CONVERSION
Resolution: 14 bits
Sampling Rate: 500 MS/s (simultaneously on each channel)
- SYSTEM PERFORMANCES
ENOB (Typ.): 10.5 (@50MHz, -3dB, Gain x2)
RMS (Typ.): 2.4 LSB RMS (@Gain x2)
- DIGITAL I/O
CLK-IN (CLK-OUT) - Two differential pairs:
- CLK, reference clock signal
- SYNC, synchronization signal (start/stop, T0, etc.)
- Daisy chainable in multi-board synchronization
- 2.54mm 4-pin AMPMODU Mod II male connector
- CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)
- CLK-OUT: LVDS
LVDS I/O - 16 differential pairs
- Sw programmable I/O function (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.)
- LVDS
- Zdiff = 100 Ω (when set as inputs)
- 2.54mm 34-pin AMPMODU Mod II male connector
TRG-IN/TRG-OUT/GPIO/S-IN - General-purpose digital I/Os
- Sigle-ended TTL/NIM
- LEMO 00 male connector
- Sw programmable function (trigger, veto, busy, etc.)
- TRG-IN/S-IN: internally terminated with 50 Ω (Zin = 50 Ω)
- TRG-OUT requires Rt = 50 Ω
- GPIO as Input must be terminated with 50 Ω
- GPIO as TTL Output requires Rt = 50 Ω
- GPIO as NIM Output requires Rt = 50 Ω or 25 Ω
- Two differential pairs:
- DAC OUT
- DAC output for signal inspection, pulse generation, majority level
- 14-bit Digital-to-Analog Converter (DAC)
- 125 MS/s Update Rate
- ±1 V @ 50Ω load; ±2 V @ hi-Z load Output Range
- LEMO 00 male connector
- ACQUISITION MEMORY
5 GB total DDR4 memory size (83.886 MS/ch) divisible in multiple buffers
Maximum record length: 84 ms @ 500 MS/s (total memory size divided by 2)11 Value referred to the Scope firmware (minimum of two buffers admitted)
- TRIGGER
Trigger Modes - Common: all channels acquire simultaneously with the trigger (software, external or logic combination of self-triggers)
- Individual: each channel acquires independently with its self-trigger
- Correlated: the individual self-trigger of each channel is validated by the coincidence/anticoincidence logic between other self-triggers and/or external I/Os
Trigger Timestamp – Scope firmware - Resolution: 8 ns coarse timestamp
- Counter range: 48 bits
- Full-scale range: ~625 h
Trigger Time Stamp (DPP firmware)
- Resolution: 2 ns coarse timestamp, 2 ps fine timestamp
- Counter range: 48 bits
- Full-scale range: ~156 h
- SYNCHRONIZATION
Clock Propagation Typical 62.5 MHz frequency distributed by daisy chain through CLK-IN/CLK-OUT or by fan-out to CLK-IN
Custom frequencies can be supportedAcquisition Start/Stop
Daisy chain or fan-out propagation through CLK-IN/CLK-OUT or NIM/TTL, LVDS I/Os
Data Sync Busy/Veto logic on LVDS I/Os or NIM/TTL I/Os for event building synchronization
Trigger Distribution
TRG-IN/TRG-OUT NIM/TTL LEMO I/Os (common trigger) or LVDS I/Os (common or individual trigger)
Trigger Time Stamp Reset
Software from START run command or Hardware from S-IN/GPIO input (Scope Firmware only)
- FIRMWARE
Firmware stored in the on-board Flash Memory and live rebootable by Web Interface
DPP Firmware Implements the digital pulse processing algorithm:
Scope Firmware Firmware for the waveform recording
Upgrades Any supported firmware can be uploaded via Web Interface (both different firmware types and upgraded versions of the same firmware)
- FPGA
- Xilinx Zynq UltraScale+ Multiprocessor System-on-Chip mod. XCZU19EG
- Processing System based on Quad-core Arm with 2GB DDR4 memory @2400 MT/s (Linux OS onboard)
- Programmable logic with more than 1100K system logic cells and 80Mbit memory
- OPEN FPGA
User-Scope Template Common trigger, simultaneous waveform recording on 64 channels management. Trigger logic and wave processing customization
User-DPP Template Individual trigger and channel acquisition management. Customization of DPP algorithm, trigger logic, and event data information
- COMMUNICATION INTERFACE
1 GbE - Copper RJ45 or optical LC connector on SFP+ transceiver
- TCP/IP protocol
- Transfer rate: 110 MB/s
10 GbE (Coming Soon)
- Copper RJ45 or LC optical connector on SFP+ transceiver
- Protocol: TCP/IP, UDP
- Transfer rate: 280 MB/s (TCP/IP), t. b. d. (UDP)
CONET (Available on Request) - Optical LC connector on SFP+ transceiver
- CONET2 protocol (CAEN proprietary)
- Transfer rate: 80 MB/s
USB 3.0
- USB-C type connector
- USB 3.1 GEN1 protocol
- Transfer rate: 280 MB/s
- SOFTWARE
Readout SW
SDK and Tools
General purpose C libraries with demo samples for host Windows® and Linux® PC, and embedded Arm processorSCI-Compiler (Open FPGA)
Automatic generation of drivers (USB, ethernet), libraries, and demo software for Windows®, Linux®Web Interface
Firmware management (e,g. upgrades and on-the-fly selection of the firmware to run), board information, PLL and Ethernet configuration, board status monitoring

- Documentation
- Software
- Firmware
Free
Data Sheet
Manuals
Application SW
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Code | Description |
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WDT2730XAAAA | DT2730 - 32 Ch. 14 bit 500MS/s Digitizer with Programmable Input Gain RoHS |