V1761
2 Channel 10 bit 4GS/s Digitizer
- 2 channel
- 10 bit 4 GS/s (interleaved) ADC
- 1 Vpp input dynamics (single ended or differential)
- 16-bit programmable DC offset adjustment (±0.5V)
- External ADC clock input or PLL synthesis from internal/external reference
- Front panel clock In/Out available for multiboard synchronisation (direct feed through or PLL based synthesis)
- 16 programmable LVDS I/Os
- Trigger Time stamps
- Memory buffer: 7.2 and 57.6 MS/ch available
- FPGA for real-time data processing
- Programmable event size and pre-post trigger adjustment
- VME64X compliant interface
- Optical Link interface
- A2818 PCI controller available for handling up to 8 Modules daisy chained via Optical Link
- Firmware upgradeable via VME/Optical Link
- Demo software
Overview
The Mod. V1761 is a 1-unit wide VME 6U module housing a 2 Channel 10 bit 4 GS/s Flash ADC Waveform Digitizer with threshold Auto-Trigger capabilities.
Input dynamics is 1 Vpp (single ended or differential).
The DC offset adjustment (range ± 0.5V)by 16bit DACs allows a right sampling of a bipolar (Vin=± 0.5V) up to a full positive (Vin= 0 ÷ +1V)) or negative (Vin= 0 ÷ -1V) analog input swing without losing dynamic resolution.
The modules feature a front panel clock/reference In/Out and a PLL for clock synthesis from internal/external references. This allows multi board phase synchronizations to an external clock reference or to a clock Digitizer master board.
The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read either via VME or via Optical Link. The acquisition can continue without dead time in a new buffer.
Each channel has a SRAM Multi-Event Buffer divisible into 1 ÷ 1024 buffers of programmable size, with independent read-write access. Two sizes of the channel digital memory are available by ordering options: 7.2 MS/ch (mod. V1761/V1761B) and 57.6 MS/ch (mod. V1761C).
The trigger signal can be provided via the front panel input as well as via the VMEbus, but it can also be generated internally. The trigger from one board can be propagated to the other boards through the front panel Trigger Output.
An Analog Output allows to reproduce the sum of the input signals as well as the majority of the buffer occupancy.
The Modules VME interface is VME64X compliant and the data readout can be performed in Single Data Transfer (D32), 32/64 bit Block Transfer (BLT, MBLT, 2eVME, 2eSST) and 32/64 bit Chained Block Transfer (CBLT).
The boards houses a daisy chainable Optical Link able to transfer data at 80 MB/s, thus it is possible to connect up to eight ADC boards (64 ADC channels) to a single Optical Link Controller (Mod. A2818). Optical Link and VME access are internally arbitrated.
Software available (windows and Linux): CAEN provides drivers for all the different types of physical communication channels, a set of C and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:
- CAENUpgrader: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.
- CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.
Technical Specifications
- Package
1-unit wide VME 6U module
- Analog Input
2 channels, single-ended (SE) or differential. Input range: 1Vpp; Bandwidth: 1 GHz. Programmable DAC for Offset Adjust x ch. (SE only).
- Digital Conversion
Resolution: 10 bit; Sampling rate:4 GS/s simultaneously on each channel; multi board synchronization (one board can act as clock master). External Gate Clock capability (NIM/TTL) for burst or single sampling mode.
- ADC Sampling Clock generation
Two operating modes: – PLL mode – internal reference (50 MHz loc. oscillator). – PLL mode – external reference on CLK_IN (±100ppm tolerance).
- CLK_IN
AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by custom cable).
- CLK_OUT
DC coupled differential LVDS output clock, locked to ADC sampling clock. Freq.: 10 ÷ 500MHz.
- Memory Buffer
7.2 MS/ch or 57.6 MS/ch Multi Event Buffer
Divisible into 1 ÷ 1024 buffers
Independent read and write access
Programmable event size and pre-post trigger
- Trigger
Common External TRGIN (NIM or TTL) and VME CommandIndividual channel autotrigger (time over/under threshold)TRGOUT (NIM or TTL) for the trigger propagation to other boards.
- Trigger Time Stamp
32bit – 4ns (34s range). Sync input for Time Stamp alignment
- ADC and Memory controller FPGA
Four Altera Cyclone EP3C16
- Optical Link
Data readout and slow control with transfer rate up to 80 MB/s, to be used instead of VME bus. Daisy chainable: one A2818 PCI card can control and read eight boards in a chain.
- VME interface
VME64X compliantD32, BLT32, MBLT64, CBLT32/64, 2eVME, 2eSST, Multi Cast CyclesTransfer rate: 60MB/s (MBLT64), 100MB/s (2eVME), 160MB/s (2eSST).Sequential and random access to the data of the Multi Event Buffer. The Chained readout allows to read one event from all the boards in a VME crate with a BLT access.
- Upgrade
V1761 firmware can be upgraded via VME or Optical Link
- Software
General purpose C Libraries and Demo Programs (CAENScope).
- Analog Monitor
12bit / 125 MHz DAC FPGA controlled output, four operating modes:Test Waveform: 1 Vpp test ramp generatorMajority: MON/Σ output signal is proportional to the number of channels (enabled) under/over threshold (1 step = 125mV)Buffer Occupancy: MON/Σ output signal is proportional to the Multi Event Buffer OccupancyVoltage level: MON/Σ output signal is a programmable voltage level
- LVDS I/O
16 gen. purpose LVDS I/O controlled by FPGABusy, Data Ready, Memory full, Individual Trig-Out and other function can be programmed.An Input Pattern from the LVDS I/O can be associated to each trigger as an event marker.
- Input connectors
Single ended: MCX Differential: Tyco MODU II
- Power Consumption
6.5 A @ +5 V
200 mA @ +12 V
300 mA @ -12 V

- Documentation
- Software
- Firmware
Manuals
Brochures, Flyers
Application Notes
White Papers
Related Software Products
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Ordering Options
Code | Description |
---|---|
WV1761BXAAAA | V1761B - 2 Ch. 10 bit 4 GS/s Digitizer: 7.2MS/ch, EP3C16, DIFF (Obsolete) |
WV1761CXAAAA | V1761C - 2 Ch. 10 bit 4 GS/s Digitizer: 57.6MS/ch, EP3C16, SE RoHS |
WV1761XAAAAA | V1761 - 2 Ch. 10 bit 4 GS/s Digitizer: 7.2MS/ch, EP3C16, SE RoHS |