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V1761

2 Channel 10 bit 4GS/s Digitizer

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Features

  • 10-bit @ 4 GS/s
  • Analog inputs on MCX coaxial connectors (50 Ω, single-ended)
  • 2 channels, 1-unit wide 6U VME64 module
  • 1 Vpp input dynamic range with programmable DC offset adjustment
  • Time-stamped Waveform Recorder
  • Memory buffer: 7.2 MS/ch or 57.6 MS/ch size
  • Programmable event size and post-trigger adjustment
  • VME64 (VME64X compliant) and Optical Link communication interfaces
  • Multi-board synchronization features
  • 16 programmable LVDS I/Os
  • Daisy chain capability
  • Compliant with CAEN WaveDump, C and LabVIEW Libraries
More info
3 Years Warranty
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Overview

The Mod. V1761 is the CAEN Waveform Digitizer with the highest sampling rate Flash ADC (10 bit @ 4GS/s).

It can record fast signals from fast organic, inorganic and liquid scintillators coupled to PMTs or Silicon Photomultipliers, Diamond detectors and others, and save them with high efficiency and precision for offline advanced timing analysis. The acquisition can be externally vetoed/gated. Multiple boards can be synchronized to build up complex systems.

The data stream is written in a circular memory buffer with independent read/write access, which reduces the dead-time of the acquisition process.

The acquisition is fully controlled by CAEN WaveDump software, which manages the settings, plots and saves the waveforms. Libraries and demo software in C and LabView are available for integration and customization of specific acquisition systems.

The V1761 comes in a VME form factor with 2 input channels. The communication to and from the board is provided through VMEBus and Optical Link interfaces.

The V1761 fits in the single-slot CAEN VME64X u-crate, which allows you to convert the VME digitizer into a desktop board for lab tests.

Technical Specifications

GENERAL

Form Factor: 1-unit wide, 6U VME64

ANALOG INPUT

Channels: 2 channels single-ended
Bandwidth: 1 GHz
Impedance: 50 Ω
Connector: MCX
Full Scale Range: 1 Vpp
Offset: Programmable DAC for DC offset adjustment in the full-scale range

DIGITAL CONVERSION

Resolution: 10 bits
Sampling Rate: 4 GS/s Simultaneously on each channel

ADC CLOCK GENERATION
  • Clock source: internal/external
  • Onboard programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference
DIGITAL I/O
CLK-IN (AMP Modu II)
AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by CAEN adapter)
Jitter<100 ppm requested

CLK-OUT (AMP Modu II)
DC coupled LVDS output clock for multi-board synchronization
TRG-OUT (LEMO)
Local trigger digital output
NIM/TTL, Rt = 50 Ω



TRG-IN (LEMO)
External trigger digital input
NIM/TTL, Zin = 50 Ω
S-IN (LEMO)
SYNC/START front panel digital input
NIM/TTL, Zin = 50 Ω
ACQUISITION MEMORY
  • 7.2 MS/ch (1.9 ms @ 4 GS/s) or 57.6 MS/ch (15 ms @ 4 GS/s) Multi-event Buffer divisible into 1 ÷ 1024 buffers
  • Independent read and write access
  • Programmable event size and pre/post-trigger
TRIGGER
Trigger Source
Self-trigger: channel over/under threshold for Common trigger generation
External-trigger: Common by TRG-IN connector
Software-trigger: Common by software command
Trigger Time Stamp
Waveform Recording: 31-bit counter, 16 ns resolution, 17 s range; 48-bit extension by firmware

Trigger Propagation
TRG-OUT digital output
SYNCHRONIZATION
Clock Propagation
Daisy chain: CLK-IN/CLK-OUT connectors
One-to-many: clock distribution from DT4700 on CLK-IN connector
Clock Cable delay compensation
Acquisition Synchronization
Sync Start/Stop through digital I/O (S-IN or TRG-IN input, TRG-OUT output)
Trigger Time Stamp Alignment
By S-IN input connector
ADC & MEMORY CONTROLLER FPGA

Four Altera Cyclone III EP3C16

ANALOG MONITOR

12-bit/125 MHz DAC FPGA controlled output with four operating modes:
Test pulses: 1 Vpp ramp generator
Majority signal: proportional to the no. of channels under/over the threshold (steps of 125 mV)
Memory Occupancy signal: proportional to the Multi-Event Buffer Occupancy (1 buffer ~ 1mV)
Voltage level: programmable output voltage level

LVDS I/O

16 general purpose LVDS I/Os controlled by FPGA
Busy, Data Ready, Memory Full, Individual Trg-Out and other functions can be programmed
An Input Pattern from the LVDS I/Os can be associated to each trigger as an event marker

COMMUNICATION INTERFACE
VME
VME 64X compliant
Data transfer mode: BLT32, MBLT64 (70 MB/s using CAEN Bridge), CBLT32/64, 2eVME, 2eSST (up to 200 MB/s)
Optical Link
CAEN CONET proprietary protocol, up to 80 MB/s transfer rate
Daisy chainable: it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod.A2818/A3818)
FIRMWARE

Waveform Recording Firmware: Free firmware for waveform recording
Upgrades: Firmware can be upgraded via Optical Link or VMEBus

SOFTWARE

Libraries: General purpose C and LabVIEW Libraries
Readout Software: CAEN WaveDump
Configuration Tools: CAEN Upgrader for Firmware upgrade. Direct Register R/W (Example codes)

POWER REQUIREMENTS
  • 6.5 A @ +5 V
  • 200 mA @ +12 V
  • 300 mA @ -12 V

Compare

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Accessories

A654
Cable assembly LEMO 00 male to MCX male – 1 m
A659
Cable assembly BNC male to MCX male – 1 m
AI2700
Optical Fiber Series
A317
Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm
A318
Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
A316
Cable assembly 2.54mm 2-pin header female - 5 cm
A952
Cable assembly 2.54mm 34 pin female to 2.54mm 34 pin female - 50 cm
A953
Cable assembly 2.54mm 34 pin female to two 2.54mm 34 pin female – 50 cm
A954
Cable assembly 2.54mm 34 pin female to two 2.54mm 16 pin female - 50 cm

Ordering Options

Code Description
WV1761BXAAAA V1761B - 2 Ch. 10 bit 4 GS/s Digitizer: 7.2MS/ch, EP3C16, DIFF  (Obsolete)
WV1761CXAAAA V1761C - 2 Ch. 10 bit 4 GS/s Digitizer: 57.6MS/ch, EP3C16, SE   RoHS
WV1761XAAAAA V1761 - 2 Ch. 10 bit 4 GS/s Digitizer: 7.2MS/ch, EP3C16, SE   RoHS

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