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V1743

16 Channel 12bit 3.2 GS/s Switched Capacitor Digitizer

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Features

  • 12-bit @ 3.2 GS/s, 1024 samples per event
  • Developed in collaboration with CEA/IRFU & CNRS/IN2P3/LAL and based on the SAMLONG chip
  • 3.2, 1.6, 0.8, 0.4 GS/s software selectable sampling frequencies
  • Analog inputs on MCX coax. connectors
  • 16 channels in 1-unit VME 6U form factor
  • 2.5 Vpp input dynamic range with programmable individual DC offset adj.
  • One discriminator per channel with programmable threshold
  • Adjustable post-trigger delay (up to 1.25 µs @ 3.2 GS/s)
  • Digital Memory buffer: 7 events/ch
  • 1024 samples per channel (320 ns recorded time per event @ 3.2 GS/s)
  • Dead time due to event conversion: 125 µs (max. @ 1024 samples)
  • Real time hit counting independent of acquisition rate on each channel
  • On-board charge calculation for fast histogramming (user-defined integration window)
  • One embedded pulser per channel for test and reflectometry applications
  • Optical Link interface (CAEN proprietary protocol)
  • VME64X-compliant interface
  • A2818(PCI) / A3818 (PCIe) Controller available for handling up to 8/32 modules Daisy chained via Optical Link
  • Firmware upgradeable via VMEbus/Optical Link
  • Multi-board synchronization features
  • 16 programmable LVDS I/Os
  • Fully controlled by the WaveCatcher readout software
  • Drivers and libraries for Windows and Linux 32/64-bit
More info
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Overview

The CAEN Mod. V1743 is a VME 6U module housing 16 Channel 12 bit 3.2 GS/s Switched Capacitor Digitizer, with 2.5 Vpp single-ended input dynamics, issued from the collaboration with CEA/IRFU & CNRS/IN2P3/LAL and based on SAMLONG chip. A programmable DAC on each channel allows for DC Offset adjustment in the ±1.25 V range.

The analog input signals are continuously sampled into the SAMLONGs (sampling intervals down to 312.5 ps) in a circular analog memory buffer (1024 cells). As a trigger signal arrives, all analog memory buffers are frozen and subsequently digitized with a resolution of 12 bits into a digital memory buffer. During analog to digital conversion process, the V1743 cannot handle other triggers (Dead Time: 115 us).

The memory buffer allows to store up to 7 full events for each cannel (1 event = 1024x12bit). The buffer can be read by VME bus or Optical Link simultaneously with write operation of successive events.

The module features front panel Clock Input and Output, as well as a PLL for clock synthesis from internal/external references. V1743 supports multi-board synchronization allowing all switched capacitor memories to be synchronized to a common clock source and ensuring Trigger time stamps alignment. Once synchronized, all data will be aligned and coherent across multiple V1743 boards

Each channel is equipped with an individual discriminator, with programmable threshold, which generates a trigger request when the input signal goes over threshold. The trigger requests from the channels are processed by the board to generate a common trigger causing all the channels to acquire an event simultaneously. The common trigger can also be provided externally via the front panel Trigger Input or via the software, for debug purposes, through VMEbus/Optical Link

V1743 houses VME (VME64X compliant) and Optical Link interfaces. The VME interface allows data transfers of 60 MB/s (MBLT64), 100 MB/s (2eVME), 160 MB/s (2eSST). The Optical Link supports transfer rate of 80 MB/s and offers Daisy chain capability. Therefore, it is possible to connect up to 8/32 ADC modules to a single Optical Link controller (Mod. A2818/A3818).

Mod. V1743 features an embedded Charge Mode, where the pulse integration window is defined by the user (high rates ~3.5 KEvents/s). This feature allows to perform on-line processing on detector signal directly digitized.

Some typical applications:

  • Precise characterization of high speed detectors (PMTs, SiPMs, APDs,…)
  • High Resolution Photon timing with MCP-PMTs

Software available (Windows and Linux):
CAEN provides drivers for all the different types of physical communication channels, a set of C libraries (CAENComm and CAENDigitizer) for Windows and Linux OS, as well as a control software tool for Windows:

  • CAENUpgrader: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.
  • WaveCatcher: fully graphical program that implements an oscilloscope.

The V1743 fits in the single-slot CAEN VME64X u-crate, which allows you to convert the VME digitizer into a desktop board for lab tests.

Technical Specifications

MECHANICAL

Form Factor: 1‐unit wide VME64/VME64X boards
Weight: 535 g
Dimension: 6U x 160 mm

ANALOG INPUT

Channels: 16 channels single ended
Offset: Programmable 16-bit DAC for DC offset adjustment on each channel. +Range: ± 1.25 V
Impedance: 50 Ω
Absolute max analog input voltage: ±3.5 V
Connector: MCX
Full Scale Range: 2.5 Vpp DC coupled
Bandwidth: 500 MHz

TEST FUNCTION

One pulser per channel with programmable 16-bit pattern (fixed amplitude)

DIGITAL CONVERSION

Analog Memory (Switched Capacitor Array): SAMLONG Fast Analog Memory chip.
2 channels, 1024 storage cells/ch. 320 ns minimum recorded time/event

Sampling Rate: 3.2/1.6 /0.8/0.4 GS/s SW selectable, simultaneously on each channel

Resolution: 12 bits
Dead Time (Event A/D Conversion): 125 µs (max. @ 1024 samples) decreasing proportionally with the depth recording (configurable record length)

CHANNEL FPGA

Altera Cyclone EP3C16 (one FPGA manages 4 channels)

TIMING RESOLUTION

< 8 ps RMS (5 ps RMS typical) @ 3.2GS/s
Obtained at thermal regime, after INL time calibration and with dual-pulse timing measurement by pulse generator
Test conditions: periodic input pulses with 1V Amplitude, 1kHz Frequency, rise time of 0.8/1.6/2.5 ns; the resolution does not change significantly when varying the delay Δt between the two pulses
Note: it is recommended to provide proper cooling to improve the resolution performances

NOISE LEVEL

0.75 mV RMS

SYSTEM PERFORMANCES
Sampling Time Precision

< 20 ps @ 3.2 GS/s (before calibration)
< 5 ps @ 3.2 GS/s (after calibration)
Note: obtained with factory calibration and dual-pulse timing measurement with pulse generator.
Test conditions:
– Periodic input pulses with 1-V Amplitude,
– 1-kHz Frequency,
– Rise time of 0.8 / 1.6 / 2.5 ns.

The resolution does not change significantly when varying the delay Δt between the two pulses.

 Noise Level

0.75 mV RMS
ADC CLOCK GENERATION

Synchronization clock source: internal/external
On-board PLL provides generation of the main board clocks from an internal (50 MHz loc. oscillator) or external (front panel CLK-IN connector) reference

ACQUISITION MEMORY
  • 7 full event/ch Multi‐event buffer (1024 S/event, that is 320 ns/event @ 3.2 GS/s)
  • Independent read and write access
  • Programmable event size and pre/post‐trigger
TRIGGER

Trigger Source
• Self-trigger: channel over/under threshold (based on analog discriminator on each channel with DAC adjusted threshold) for Common trigger generation
• External-trigger: common trigger by TRG-IN connector
• Software-trigger: common trigger by software command
Trigger Propagation TRG-OUT programmable digital output
Trigger Time Stamp 40-bit counter, 5-ns resolution, 83-min range Timer reset by S-IN input connector
Trigger Threshold Programmable through a 16-bit DAC in the range of ±1.25 V on each channel

SYNCHRONIZATION
Clock Propagation

Daisy chain: through CLK-IN/CLK-OUT connectors.
One‐to‐many: clock distribution from an external clock source to CLK‐IN connector.
Clock Cable delay compensation

Acquisition Synchronization

Sync, Start/Stop through LVDS I/Os

 Trigger Time Stamps Alignment

By S-IN input connector

Data Alignment

Busy/Veto through LVDS I/Os
ADC & MEMORY CONTROLLER

Altera Cyclone EP3C16 (1 FPGA serves 4 channels)

COMMUNICATION INTERFACE

Optical Link: CAEN CONET proprietary protocol, up to 80 MB/s transfer rate. Daisy chainable: it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod.A2818/A3818)
VME: VME 64X compliant. Data transfer mode: BLT32, MBLT64 (70 MB/s using CAEN Bridge), CBLT32/64, 2eVME, 2eSST (up to 200 MB/s)

ANALOG MONITOR

12-bit / 125 MHz DAC, FPGA-controlled, provides a Trigger Majority signal on the MON/Σ front panel connector, proportional to the number of the over-threshold channels (in steps of 125 mV)

LVDS I/O

16 general purpose LVDS I/O controlled by the FPGA: Data Ready, Memory full, Memory Clear, TTT reset and other functions available.
An Input Pattern from the LVDS I/O can be associated to each trigger as an event marker

DIGITAL PULSE PROCESSING

Software selectable embedded Charge Mode for input pulse high rate charge integration and fast histogramming

FIRMWARE

Normal Mode (default): Waveform recording
Charge Mode (sw selectable): Input pulse high-rate charge integration
Upgrades: Supported via VMEbus/Optical Link

SOFTWARE
Readout SW

  • WaveCatcher (Windows® only)
  • WaveDemo_x743 (Windows®, Linux®) including C source files and VS project
 Libraries and Tools

General purpose C libraries (Windows®, Linux®) Configuration tools
POWER CONSUMPTIONS

4 A @ +5 V
625 mA @ +12 V
-12 V not used

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Ordering Options

Code Description
WV1743XAAAAA V1743 - 16 Ch. 12 bit 3.2GS/s Switched-Capacitor Digitizer: 7 events/ch (1kS/event), EP3C16, SE   RoHS

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