V1741

Overview

The V1741 is a Digital Peak Sensing ADC belonging to a new generation of detector readout systems based on a mixed analog-digital acquisition chain, combining a high channel density (64 channels) and a low dead time. The FLASH ADC architecture makes it possible to achieve an extremely low conversion time of the pulse peak, so new conversions take place less than 50 ns after the previous gates close.

Conversion gain ranges from 1k up to 16k channels with a low differential non-linearity (DNL) thanks to the sliding scale method.

Receiving the typical slow signal from a Charge Sensitive Preamplifier followed by a Shaping Amplifier (e.g. CAEN N1068), the FPGA identifies the peak of the pulse within a gate by means of digital filters. The acquisition is common to all channels and takes place as soon as the GATE arrives. The energy value together with the time of arrival of the event is first stored in a 1024 multi-event buffer and made available for the readout by VME bus or optical link interface (Daisy-chainable). Both the energy spectrum and the list of events is available through the software interface. Data throughput can be reduced by the Zero Suppression algorithm with a programmable threshold.

The front panel hosts LEMO (NIM/TTL) inputs that can be used for the GATE, the event discard in case of pile-up (REJ), and the GATE propagation (GPO). The Gate can be linear (same width as the external signal) or re-formed with programmable width.

The V1741 is provided with drivers for the supported communication interfaces, C libraries, demo software for an easy board understanding. Firmware upgrade can be performed via optical link or VMEbus by the user.