V1741
New
64 Ch Peak Sensing ADC
- 1-unit 6U VME Module
- 1k, 2k, 4k 8k, 16k Peak Sensing ADC
- 64 input channels, single ended, ERNI SMC (Zin: 1 kΩ)
- Low dead time (re-triggering less than 100 ns after the previous gate closes)
- Sliding scale algorithm for DNL reduction over 1/16 of the full ADC scale
- 4 Vpp Full Scale Range (3.75 Vpp with sliding scale enabled)
- Full-scale INL < 0.05% over 1 : 99% FSR
- Accepts positive and negative inputs
- Zero suppression with programmable threshold
- Multi-Event Buffer (512 event/channel)
- Common Gate mode (64 channels converted at once) with linear gate width or programmable by software
- Individual Gate mode with 64 independent self-gating channels
- Fast Clear input for the event discard (PUR)
- Extended Time Stamp (48 bit)
- Internal dead-time counters
- VME64/VME64x and Optical link (CAEN CONET proprietary protocol) communication interfaces
- Multi-board synchronization and Daisy chain capabilities
- Windows and Linux drivers, C and LabVIEW libraries, demo software and firmware upgrade tool
- Firmware upgradable by the user
- 2 models available:
- V1741 (1-unit wide 6U VME)
- VX1741 (1-unit wide 6U VME64X)
Overview
The V1741 (VX1741) is a Digital Peak Sensing ADC belonging to a new generation of detector readout systems based on a mixed analog-digital acquisition chain, combining a high channel density (64 channels) and a low dead time.
Conversion gain ranges from 1k up to 16k channels with a low differential non linearity (DNL) thanks to the sliding scale method.
The FLASH ADC architecture makes possible to achieve an extremely low conversion time of the pulse peak, so new conversions take place less than 100 ns after the previous gates close.
Receiving the typical slow signal from a Charge Sensitive Preamplifier followed by a Shaping Amplifier, the FPGA identifies the peak of the pulse within a gate by means of digital filters. The energy data are stored with the time stamp in a multi-event buffer and are available for the readout by VME bus or optical link interface (Daisy-chainable). Data throughput can be reduced by the Zero Suppression algorithm with programmable thresholds.
The front panel hosts LEMO (NIM/TTL) inputs for the Gate and for the event discard during the acquisition in case of pile-up. The Gate can be linear (same width as the external signal) or re-formed with programmable width. Specific I/Os allow for multi-board synchronization and for Gate propagation.
The V1741 is provided with drivers for the supported communication interfaces, C and LabVIEW libraries, demo software for an easy board understanding. Firmware upgrade can be performed via optical link or VMEbus by the user.
Technical Specifications
- GENERAL
Form Factor
1-unit wide VME 6U module
Weight
535 g
- ANALOG INPUT
Channels 64 channels
Single ended
Connector 64-pin Dual Row ERNI SMC
Bandwidth 30 MHz
Impedance Zin = 1 kΩ
Full Scale Range (FSR) 4 Vpp (3.75 Vpp with sliding scale enabled) or 8 Vpp (default)
SW selectable
Offset The Sliding Scale automatically manages the DAC for DC offset adjustment on each channel.
- DIGITAL CONVERSION
Resolution
12 bitsSampling Rate
62.5 MS/s simultaneously on each channel
- CONVERSION GAIN
1k, 2k, 4k, 8k, 16k
- DEAD TIME
< 100 ns
- INTEGRAL NON LINEARITY (INL)
< 0.05% over 1 : 99% FSR
- DIFFERENTIAL NON LINEARITY (DNL)
< 1%
- ZERO SUPPRESSION
Common thresholds to 8 channels groups and programmable in: ADC counts step over the entire FSR
- GATE
Gate mode with linear gate width or programmable by software
- MEMORY
Multi-event Buffer (512 event/channel)
- DIGITAL I/O
CLK-IN (AMP Modu II) AC coupled differential input clock
LVDS, ECL, PECL, LVPECL, CML
(single ended NIM/TTL available by A318 adapter)
Jitter<100ppm requested
GATE (LEMO)
External trigger digital input
NIM/TTL; Zin = 50 Ω
CLK-OUT (AMP Modu II) DC coupled differential
LVDS clock output locked at
ADC sampling clock
GPO (LEMO)
Trigger digital output
NIM/TTL; Rt = 50 Ω
REJ (LEMO) front panel digital input
NIM/TTL
Zin = 50 Ω
- TRIGGER
Trigger Source Self-trigger (T.B.D.): channel over/under-threshold for Common Trigger generation
External-trigger: Common by TRG-IN connector
Software-trigger: Common by software command
Trigger Propagation TRG-OUT programmable digital output
Trigger Time Stamp
31-bit counter, 16 ns resolution, 17 s range;48-bit extension by firmware
- LVDS I/O
16 general purpose LVDS I/O controlled by the FPGA: Run, Busy, Veto, Trigger and other functions can be programmed
An Input Pattern from the LVDS I/O can be associated to each trigger as an event marker
- ADC & MEM. CONTROLLER
Altera Cyclone EP1C16 (one FPGA serves 16 channels)
- SYNCHRONIZATION
Clock Propagation
Daisy chain:through CLK-IN/CLK-OUT
connectors
One-to-many: clock distribution from an
external clock source on CLK-IN connector
Clock Cable delay compensation
- COMMUNICATION INTERFACE
Optical Link CAEN CONET proprietary protocol
Up to 80 MB/s transfer rate
Daisy chainable: it is possible to
connect up to 8 or 32 ADC modules to a
single Optical Link Controller (respectively A2818 or A3818)
VME VME 64X compliant
Data transfer mode: BLT32, MBLT64
(70 MB/s using CAEN Bridge),
CBLT32/64, 2eVME, 2eSST (up to 200 MB/s)
- DPP FW SUPPORTED
Peak Sensing firmware
- FIRMWARE UPGRADE
Firmware can be upgraded via VMEbus/Optical Link
- SOFTWARE
General purpose C libraries, configuration tools, readout software (Windows and Linux support)
- POWER CONSUMPTIONS
5.6 A @ +5V; 250 mA @ +12V, -12V not used
Compare
Compare with ADCs (Peak Sensing).
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Ordering Options
| Code | Description |
|---|---|
| WV1741XAAAAA | V1741 64ch Peack Sensing ADC RoHS |
