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V1740D

64 Channel 12 bit 62.5 MS/s Digitizer supporting DPP-QDC firmware

Features

  • 12 bit 62.5 MS/s ADC
  • 64 channels
  • Two ERNI SMC Dual Row 68pin connectors (32 + 32 channels)
  • 2 Vpp single ended input range
  • 16-bit programmable DC offset adjustment: ±1 V
  • Trigger Time stamps
  • Memory buffer: 192 kS/ch, up to 1024 events
  • FPGA for real-time data processing:
  • Programmable event size and pre-post trigger adjustment
  • Analog Sum/Majority and digital over/under threshold flags for Global Trigger logic
  • Front panel clock In/Out available for multiboard synchronisation (direct feed through or PLL based synthesis)
  • 16 programmable LVDS I/Os
  • Optical Link interface (CAEN proprietary protocol)
  • VME64X compliant interface
  • A2818 (PCI) / A3818 (PCIe) Controller available for handling up to 8/32 modules Daisy chained via Optical Link
  • Firmware upgradeable via VME/Optical Link
  • Libraries, Demos (C and LabView) and Software tools for Windows and Linux

Overview

The Mod. V1740D is a 1-unit wide VME 6U module housing a 64 Channel 12 bit 62.5 MS/s (65 MS/s using external clock) Flash ADC Waveform Digitizer and featuring 2 Vpp single ended input dynamics on two ERNI SMC connectors.
The DC offset adjustment (range ±1 V) by programmable 16bit DACs (one for each 8-channel group) allows a right sampling of a bipolar (Vin = ±1 V) up to a full positive (Vin = 0 ÷ +2 V) or negative (vin = 0 ÷ -2 V) analog input swing without losing dynamic resolution.
The module features front panel Clock Input and Output as well as a PLL for clock synthesis from internal/external references. The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read either by VMEbus or Optical Link. The acquisition can continue without dead time in a new buffer.

Each channel has a SRAM Multi-Event Buffer divisible into 1 ÷ 1024 buffers of programmable size. The readout (by VMEbus or Optical Link) of a frozen buffer is independent from the write operations in the active buffer (ADC data storage). Each channel has a SRAM Multi-Event Buffer of 192 kS divisible into 1.

V1740D supports multi-board synchronization allowing all ADCs to be synchronized to a common clock source and ensuring Trigger time stamps alignment. Once synchronized, all data will be aligned and coherent across multiple V1740D boards.

The trigger signal can be provided externally via the front panel Trigger Input as well as via the software, but it can also be generated internally thanks to threshold self-trigger capability. The trigger from one board can be propagated to the other boards through the front panel Trigger Output.

An Analog Output is available with four operating modes supported:

  • Waveform Generator: 1 Vpp ramp generator
  • Majority: output signal is proportional to the number of channels groups under/over threshold (1 step = 125 mV)
  • Buffer Occupancy: output signal is proportional to the Multi Event Buffer Occupancy: 1 buffer ~ 1 mV
  • Voltage level: output signal is a programmable voltage level

V1740D houses VME (VME64X compliant) and Optical Link interfaces. The VME interface allows data transfers of 60 MB/s (MBLT64), 100 MB/s (2eVME), 160 MB/s (2eSST). The Optical Link supports transfer rate of 80 MB/s and offers Daisy chain capability. Therefore, it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod. A5818).

Software available (Windows and Linux):
CAEN provides drivers for all the different types of physical communication channels, a set of C and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:

  • CAENUpgrader: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.

Standard Firmware compliant:

  • CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.

Digital Pulse Processing firmware for Physics Applications – this special firmware allows to perform on-line processing on detector signal directly digitizer:

Supported third-party software:

  • FSUDAQ – Florida State University DAQ

Technical Specifications

General
Form Factor
1-unit wide, 6U VME64
Weight
535 g
Analog Input
Channels
64 channels Single ended

Impedance

50 Ω @2Vpp
1 kΩ @10Vpp
Connector
64-pin Dual Row ERNI SMC

Full Scale Range

2 Vpp or 10 Vpp
Bandwidth
30 MHz

Offset

Programmable DAC for DC
offset adjustment on each
channel in the full range
(÷1V@2Vpp ÷5V@10Vpp)

Abs Max Rating (@2Vpp)
6 Vpp (with Vrail max +6 V
or –6 V) for any DAC offset
value

Digital Conversion
Resolution
12 bits
Sampling Rate
62.5 MS/s simultaneously on each channel
System Performance
ENOB
11.20 (48 kS Buffer)

SFDR

94.9 dB
THD
87.10 dB

SIGMA
0.50 LSB rms
SINAD
69.20 dB
(48 kS Buffer, open input)

ADC Sampling Clock generation

Clock source: internal/external
On-board programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference

Digital I/O
CLK-IN (AMP Modu II)
AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by custom cable)
Jitter<100ppm

CLK-OUT (AMP Modu II)
DC coupled differential
LVDS clock output locked
to ADC sampling clock,
Zdiff = 100 Ω
TRG-OUT (LEMO)
External trigger or veto
digital input: NIM/TTL
Zin = 50 Ω

TRG-IN (LEMO)

Multipurpose digital
output (e.g. trigger, busy):
NIM/TTL
Rt = 50 Ω
S-IN (LEMO)
SYNC/START
front panel digital input NIM/TTL
Zin = 50 Ω
Memory
  • 192k sample/ch
  • Multi Event Buffer divisible into 1 ÷ 1024
  • Independent read and write access
  • Programmable event size and pre/post trigger
Trigger
Trigger Source
Self-trigger: channel over/under threshold for either Common or Individual (DPP only) trigger generation
External-trigger: common trigger by TRG IN connector or individual by LVDS connector (DPP firmware only)
Software-trigger: common trigger by software command

Trigger Propagation

TRG-OUT programmable digital output
Trigger Time Stamp
Waveform Recording: 31-bit counter – 16 ns resolution – 17 s range; 48 bit fw extension
DPP-QDC: 32-bit counter – 16 ns resolution – 68 s range; 48 bit fw extension; 64 bit sw extension
Synchronization
  • Clock Propagation
    Daisy Chain: trough CLK-IN/CLK-OUT connectors
    One-to-many: clock distribution from an external clock source on CLK-IN connector
    Clock Cable delay compensation
  • Acquisition Synchronization
    Sync, Start/Stop through digital I/O (S-IN or TRG-IN input / TRG-OUT output)
  • Trigger Time Stamp Alignment
    By S-IN input connector
Trigger Time Stamp

31-bit counter, 16 ns resolution, 17 s range(*)
(*)Trigger Logic and Trigger Time Stamp counter operate at 125 MHz (i.e. 8 ns or 1/2 ADC clock cycles), while the counter value is read at a frequency of 62.5 MHz (i.e. 16 ns).

Multi Modules Synchronization
  • Clock propagation: by Daisy chain or Fan Out
  • Trigger propagation: by Daisy chain or Fan Out
  • Time stamp synchronization
ADC and Memory controller FPGA

One Altera Cyclone EP3C40 per 16 channels

Analog Monitor

12 bit/100 MHz DAC FPGA controlled output with four operating modes:

  • Test Waveform: 1 Vpp test ramp generator
  • Majority: MON/Σ output signal is proportional to the number of channels groups (enabled) under/over threshold (1 step = 125 mV)
  • Buffer Occupancy: MON/Σ output signal is proportional to the Multi Event Buffer Occupancy
  • Voltage level: MON/Σ output signal is a programmable voltage level
LVDS I/O
  • 16 general purpose LVDS I/Os controlled by FPGA
  • Busy, Data Ready, Memory full, Individual Trig-Out and other functions can be programmed
  • An Input Pattern from the LVDS I/Os can be associated to each trigger as an event marker
VME interface

VME64X compliant
Data modes: D32, BLT32, MBLT64, CBLT32/64, 2eVME, 2eSST, Multi Cast Cycles
Transfer rate: 60 MB/s (MBLT64), 100 MB/s (2eVME), 160 MB/s (2eSST)
Sequential and random access to the data of the Multi Event Buffer
The Chained readout allows to read one event from all the boards in a VME crate with a BLT access

Optical Link

CAEN CONET proprietary protocol Up to 80 MB/s transfer rate
Daisy‐chain: it is possible to connect up to 8 or 32 ADC modules to a single Optical Link Controller (respectively A2818/A4818 or A3818/A5818)

Upgrade

Firmware can be upgraded via VMEbus or Optical Link

Software
  • CoMPASS Multiparametric Acquisition Software
  • Caen DPP-QDC demo software (windows only) with C source file for developers
Ventilation Requirements

V1740D cannot operated with CAEN crates VME8001/8002/8004/8004A (weak cooling air flow)

Power Consumption

5.6 A @ +5V; 250 mA @ +12V, -12V not used

Compare

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Accessories

A317
Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm
A318
Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
A371
Adapter 2.54mm 34x2 pin male to 1.27mm 68-pin ERNI SMC female
A4818
USB 3.0 to CONET2 Adapter
A746B
Patch panel 64x LEMO 00 female to two x 1.27mm 68-pin ERNI SMC female
AI2700
Optical Fiber Series

Ordering Options

Code Description
WV1740DXAAAA V1740D - 64 Ch. 12 bit 62.5 MS/s Digitizer: 192kS/ch, EP3C40, SE   RoHS

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