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16 Channel 14 bit 1 GS/s Digitizer with programmable Input Gain


  • 14 bit @ 1 GS/s ADC
  • 16 single-ended analog inputs on MCX connectors
  • 2Vpp input range with software selectable analog gain
  • Open FPGA programming through the graphical tool SCI-Compiler
  • Wide range of applications (from Nuclear and Particle Physics to High Timing Resolution, Fast Neutron Spectroscopy, Dark Matter and Astroparticle, Fusion Plasma diagnostic, and Homeland Security)
  • Suited for signals from fast organic, inorganic and liquid scintillators coupled to PMTs or SiPMs, Diamond detectors and others
  • On-board live selection between scope mode (common trigger) and DPP mode (independent channel self-trigger)
  • Wide selection of DPP algorithms (e.g. PSD, ZLE)
  • Multiboard Synchronization and system-building capabilities
  • Front panel fully programmable I/Os (4 LEMO TTL/NIM and 16 LVDS)
  • Special 125MS/s 14-bit DAC output (LEMO) for signal inspection or trigger sum
  • On-board Zynq® UltraScale+™ FPGA with embedded Linux-based ARM® processor
  • 5GB of total acquisition memory (DDR4)
  • USB-3.0 type-C and 1/10 Gigabit Ethernet or optional CONET (CAEN daisy chainable Optical Link protocol) interfaces
  • Fully supported by CoMPASS and WaveDump2 readout software
  • SDK for embedded Linux processor and host PC


The VX2751 Digitizer is a 16-channel digital signal processor for radiation detectors in the VME64X form factor. It offers not only waveform digitization and recording but also Multi-Channel Analysis for a complete range of applications like nuclear and particle physics, high-timing resolution, Fast Neutron Spectroscopy, and Homeland Security. It is compliant with fast signals typically coming from organic, inorganic, and liquid scintillators coupled to PMTs or SiPMs, as well as Diamond detectors.

The VX2751 can perform different types of signal processing, basing on algorithms like charge integration and pulse shape discrimination (PSD), constant fraction timing (CFD), and zero-length encoding (ZLE). The algorithm parameters can be set individually for each channel or globally for all channels on the board.

Each channel of the module digitizes the analog input, which can be the signal coming from a physics detector, with a 14-bit 1GS/s ADC. The sampled data are used to initiate the digital pulse processing sequence, managed in the FPGA at the firmware level. Different firmware types can be stored at once on-board and then selected via software, according to the specific setup and acquisition mode.

  • Common trigger: All channels acquire simultaneously with a common trigger. The trigger can be fed externally or generated by a combination of individual channel discriminators. This mode is mainly intended for the acquisition of waveforms, like a digital oscilloscope. Options for zero suppression are available to remove not significant data.
  • Independent trigger: Suited mode for trigger-less applications, where no global trigger is needed but each channel acquires waveforms upon its self-trigger which fires through a digital discriminator, independently of the others.
  • DPP: Real-time processing in the FPGA allows for the extraction of physical parameters from the waveform (e.g. charge, timestamp, PSD), well suited for high counting rate applications. It is yet possible to save both raw waves and parameters.

CAEN provides closed firmware solutions for Scope (waveforms) and DPP modes, as well as a firmware generation and compiling tool for customers who want to personalize the acquisition to implement custom algorithms for pulse processing in the open FPGA. The user can have control of the data output information and customize the trigger logic to get several combinations of self-triggers and I/O signals to validate or discard the events. The Linux-based Arm processor embedded in the onboard CPU makes it possible to run automated user routines. Multi-board synchronization can be implemented via backplane or front panel easy-cabling options. Multiple communication interfaces offer flexible readout options: USB 3.0 type-C and 1/10 Gigabit Ethernet or optional Optical (CONET – CAEN Daisy Chainable Optical Link Protocol) Links.

The VX2751 fits in the single-slot CAEN VME64X u-crate, which allows you to convert the VME digitizer into a desktop board for lab tests.

Moreover, you can check this FAQ to see which CAEN VME crates are suitable for this product.

Technical Specifications


Weight:  t.b.d.
Dimension: 6U x 160 mm


Channels: 16 channels; Single-ended;
Bandwidth (-3dB): 500 MHz
Impedance: 50 Ω
Gain: SW programmable x1, x2, x4, x8, x10
Connector: MCX
Full Scale Range: 2 Vpp ÷ 0.2 Vpp
DC Offset: Individual offset adjustable in the ±1V range


Resolution: 14 bits
Sampling Rate: 1 GS/s (simultaneously on each channel)


ENOB (Typ.): t.b.d.
RMS (Typ.): t.b.d.


  • Two differential pairs:

o  CLK, reference clock signal

o  SYNC, synchronization signal (start/stop, T0, etc.)

  • Daisy chainable in multi-board synchronization
  • 2.54mm 4-pin AMPMODU Mod II male connector
  • CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)

  • 16 differential pairs
  • Sw programmable I/O function (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.)
  • LVDS
  • Zdiff = 100 Ω (when set as inputs)
  • 2.54mm 34-pin AMPMODU Mod II male connector

  • General-purpose digital I/Os
  • Sigle-ended TTL/NIM
  • LEMO 00 male connector
  • Sw programmable function (trigger, veto, busy, etc.)
  • TRG-IN/S-IN: internally terminated with 50 Ω (Zin = 50 Ω)
  • TRG-OUT requires Rt = 50 Ω
  • GPIO as Input must be terminated with 50 Ω
  • GPIO as TTL Output requires Rt = 50 Ω
  • GPIO as NIM Output requires Rt = 50 Ω or 25 Ω
  • Sw programmable DAC output for signal inspection, pulse generation, majority level
  • 14-bit Digital-to-Analog Converter (DAC)
  • 125 MS/s Update Rate
  • LEMO 00 connector
  • ±1 V @ 50Ω load
  • ±2 V @ hi-Z load Output Range
  • 5 GB total DDR4 memory size (83.886 MS/ch) divisible in multiple buffers
  • Maximum record length: 84 ms @ 1 GS/s (total memory size divided by 2)1

(1) Value referred to the Scope firmware (minimum of two buffers admitted)

1 GbE

  • Copper RJ45 or optical LC connector on SFP+ transceiver
  • TCP/IP protocol
  • Transfer rate: 110 MB/s


10 GbE

  • Copper RJ45 or LC optical connector on SFP+ transceiver
  • Protocol: TCP/IP, UDP
  • Transfer rate: 280 MB/s (TCP/IP), t. b. d. (UDP)
CONET (Available on Request)

  • Optical LC connector on SFP+ transceiver
  • CONET2 protocol (CAEN proprietary)
  • Transfer rate: 80 MB/s


USB 3.0

  • USB-C type connector
  • USB 3.1 GEN1 protocol
  • Transfer rate: 280 MB/s
Trigger Modes

  • Common: all channels acquire simultaneously with the trigger (software, external or logic combination of self-triggers)
  • Individual: each channel acquires independently with its self-trigger
  • Correlated: the individual self-trigger of each channel is validated by the coincidence/anticoincidence logic between other self-triggers and/or external I/Os
Trigger Timestamp – Scope firmware

  • Resolution: 8 ns coarse timestamp
  • Counter range: 48 bits
  • Full-scale range: ~625 h
Trigger Timestamp – DPP firmware

  • Resolution: 1 ns coarse timestamp, 1 ps fine timestamp
  • Counter range: 48 bits
  • Full-scale range: ~78 h
Clock Propagation

Typical 62.5MHz frequency distributed by daisy chain through CLK-IN/CLK-OUT or by fan-out to CLK-IN. Custom frequencies can be supported

Acquisition Start/Stop

Daisy chain or fan-out propagation through CLK-IN/CLK-OUT or NIM/TTL, LVDS I/Os

Data Sync

Busy/Veto logic on LVDS I/Os or NIM/TTL I/Os for event building synchronization

Trigger Distribution

TRG-IN/TRG-OUT NIM/TTL LEMO I/Os (common trigger) or LVDS I/Os (common or individual trigger)

Trigger Time Stamp Reset

Software from START run command or Hardware from S-IN/GPIO input (Scope Firmware only)

  • Xilinx Zynq UltraScale+ Multiprocessor System-on-Chip mod. XCZU19EG
  • Processing System based on Quad-core Arm with 2GB DDR4 memory @2400 MT/s (Linux OS onboard)
  • Programmable logic with more than 1100K system logic cells and 80 Mbit memory

The firmware is stored in the onboard Flash Memory and live rebootable by Web Interface

DDP Firmware

Firmware implementing a digital processing algorithm (PSD, ZLE)

Scope Firmware

Firmware developed for waveform recording


Firmware files and updates can be uploaded via Web Interface


User Firmware Generator and Compiler Graphical Tool for CAEN Programmable Boards.

Scope Personalization

Customizable features of the Scope firmware:

  • Common trigger
  • Simultaneous waveform recording on 16 channels management
  • Trigger logic
  • Wave processing
DPP Personalization

Customizable features of the DPP firmware:

  • Individual trigger and channel acquisition management
  • DPP algorithm
  • Trigger logic
  • Event data information



Readout SW: CoMPASS spectroscopy software (for DPP firmware only), WaveDump2 (for Scope firmware only)

SDK and Tools: General purpose C libraries with demo samples for host Windows® and Linux® PC, and embedded Arm processor

SCI-Compiler (Open FPGA): Automatic generation of drivers (USB, ethernet), libraries, and demo software for Windows®, Linux®

Web Interface: Firmware management (e,g. upgrades and on-the-fly selection of the firmware to run), board information, PLL and Ethernet configuration, board status monitoring


Environment: Indoor use
Operating Temperature: 0°C to +40°C
Storage Temperature: -10°C to +60 °C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity 5% to 90% RH non condensing
Altitude: <2000m
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: Enclosure (desktop models), not for wet location


EMC: CE 2014/30/EU Electromagnetic Compatibility
Directive Safety: CE 2014/35/EU Low Voltage Directive


+12V: t.b.d. (Typ.)
+5V: t.b.d. (Typ.)
+3.3V: t.b.d. (Typ.)


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Code Description
WVX2751XAAAA VX2751 - 16ch 14bit 1GS/s 2Vpp SE VGA Digitizer   RoHS


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