VX1720
8 Channel 12bit 250 MS/s Digitizer
Features
- 12 bit 250 MS/s ADC
- FPGA for real time Digital Pulse Processing:
- Pulse Shape Discrimination (DPP-PSD)
- Zero Suppression (Waveform Recording Firmware)
- 8 channels
- 2 Vpp input range (single ended)
- 16-bit programmable DC offset adjustment: ±1 V
- Trigger Time stamps
- Memory buffer: 1.25 or 10 MS/ch, up to 1024 events
- Programmable event size and pre-post trigger adjustment
- Analog Sum/Majority and digital over/under threshold flags for Global Trigger logic
- Front panel clock In/Out available for multiboard synchronisation (direct feed through or PLL based synthesis)
- 16 programmable LVDS I/Os
- VME64X compliant interface
- Optical Link interface (CAEN proprietary protocol)
- A2818 (PCI) / A3818 (PCIe) Controller available for handling up to 8/32 modules Daisy chained via Optical Link
- Firmware upgradeable via VME/Optical Link
- Libraries, Demos (C and LabView) and Software tools for Windows and Linux
Overview
The VX1720 is a 1-unit wide VME64X 6U module housing a 8 Channel 12 bit 250 MS/s Flash ADC Waveform Digitizer and featuring 2 Vpp single ended input dynamics.
The DC offset adjustment (range ±1 V) by programmable 16bit DACs (one for each channel) on single ended input versions allows a right sampling of a bipolar (Vin = ±1 V) up to a full positive (Vin = 0 ÷ +2 V) or negative (Vin = 0 ÷ -2 V) analog input swing without losing dynamic resolution.
The module features front panel Clock Input and Output as well as a PLL for clock synthesis from internal/external references. The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read either by VMEbus or Optical Link. The acquisition can continue without dead time in a new buffer.
Each channel has a SRAM Multi-Event Buffer divisible into 1 ÷ 1024 buffers of programmable size. Two sizes of the channel digital memory are available by ordering options: 1.25 MS/ch (mod. VX1720E) and 10 MS/ch (mod. VX1720G). “Zero suppression” and “data reduction” algorithms allow substantial savings in data amount readout and processing, rejecting samples smaller than programmable threshold. VX1720 supports multi-board synchronization allowing all ADCs to be synchronized to a common clock source and ensuring Trigger time stamp alignment. Once synchronized, all data will be aligned and coherent across multiple VX1720 boards.
The trigger signal can be provided externally via the front panel Trigger Input as well as via the software, but it can also be generated internally thanks to threshold self-trigger capability. The trigger from one board can be propagated to the other boards through the front panel Trigger Output.
An Analog Output is available with four operating modes supported:
- Waveform Generator: 1 Vpp ramp generator
- Majority: output signal is proportional to the number of ch. under/over threshold (1 step = 125 mV)
- Buffer Occupancy: output signal is proportional to the Multi Event Buffer Occupancy: 1 buffer ~ 1 mV
- Voltage level: output signal is a programmable voltage level
VX1720 houses VME (VME64X compliant) and Optical Link interfaces. The VME interface allows data transfers of 60 MB/s (MBLT64), 100 MB/s (2eVME), 160 MB/s (2eSST). The Optical Link supports transfer rate of 80 MB/s and offers Daisy chain capability. Therefore, it is possible to connect up to 8/32 ADC modules to a single Optical Link controller (Mod. A2818/A3818).
Software available (Windows and Linux):
CAEN provides drivers for all the different types of physical communication channels, a set of C and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:
- CAENSCOPE: fully graphical program that implements a simple oscilloscope.
- CAENUpgrader: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.
- CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.
CAEN provides also for this model Digital Pulse Processing firmware for Physics Applications. This feature allows to perform on-line processing on detector signal directly digitized:
- DPP-PSD Digital Pulse Processing for Pulse Shape Discrimination
x720(*) and x751 digitizers running DPP-PSD firmware accept signals directly from the detector and implement a digital replacement of dual gate QDC, discriminator and gate generator.
(*) DPP-CI firmware and DPP-CI Control Software are no longer supported. To perform Charge Integration please refer to the DPP-PSD firmware and software
The VX1720 fits in the single-slot CAEN VME64X u-crate, which allows you to convert the VME digitizer into a desktop board for lab tests.
Technical Specifications
- Packaging
1-unit wide VME64X 6U module
- Analog Input
- 8 channels (MCX 50 Ω)
- Single ended
- Input range: 2 Vpp
- Bandwidth: 125 MHz
- Programmable DAC for Offset Adjustment x channel: ±1 V
- Digital Conversion
Resolution: 12 bit
Sampling rate: 31.25 to 250 MS/s simultaneously on each channel
- System Performance
- ENOB:
SINAD:
THD:10.14 (64 kS Buffer)
62.85 dB
74.1 dBSFDR:
SIGMA:82.0 dB
0.95 LSB rms (64 kS Buffer, open input)
- ADC Sampling Clock generation
Three operating modes:
- PLL mode: internal reference (50 MHz loc. oscillator)
- PLL mode: external reference on CLK_IN
- PLL Bypass mode: ext. clock on CLK_IN drives directly ADC clocks (Freq.: 31.25 ÷ 250 MHz)
- Digital I/O
CLK_IN (AMP Modu II):
- AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by custom cable)
- Jitter < 100 ppm
CLK_OUT (AMP Modu II):
- DC coupled differential LVDS clock output locked at ACD sampling clock (Freq.:31.25 – 250 MHz)
- TRG_IN (NIM/TTL, Zin = 50 Ω): external trigger input
- TRG_OUT (NIM/TTL, Rt = 50 Ω): local trigger output
- S_IN (NIM/TTL, Zin = 50 Ω): SYNC/SAMPLE/START front panel input
- Acquisition Memory
- 1.25 MS/ch (5 ms @ 250 MS/s) or 10 MS/ch (40 ms @ 250 MS/s) Multi Event Buffer divisible into 1 ÷ 1024 buffers
- Independent read and write access
- Programmable event size and pre/post-trigger
- Trigger
Common Trigger:
- External (signal on TRG_IN)
- Software (by VMEbus or Optical Link)
- Self trigger (internal threshold self-trigger)
- Trigger Time Stamp
31-bit counter – 16 ns resolution – 17 s range
- Multi Modules Synchronization
- Clock propagation: by Daisy chain or Fan out
- Trigger propagation: by Daisy chain or Fan out
- Time stamp synchronization
- Analog Monitor
12 bit/100 MHz DAC FPGA controlled output with four operating modes:
- Test Waveform: 1 Vpp test ramp generator
- Majority: MON/Σ output signal is proportional to the number of channels (enabled) under/over threshold (1 step = 125 mV)
- Buffer Occupancy: MON/Σ output signal is proportional to the Multi Event Buffer Occupancy
- Voltage level: MON/Σ output signal is a programmable voltage level
- ADC and Memory controller FPGA
One Altera EP1C20 per channel
- LVDS I/O
- 16 general purpose LVDS I/Os controlled by FPGA
- Busy, Data Ready, Memory full, Individual Trig-Out and other functions can be programmed
- An Input Pattern from the LVDS I/Os can be associated to each trigger as an event marker
- VME interface
VME64X compliant
- Data modes: D32, BLT32, MBLT64, CBLT32/64, 2eVME, 2eSST, Multi Cast Cycles
- Transfer rate: 60 MB/s (MBLT64), 100 MB/s (2eVME), 160 MB/s (2eSST)
- Sequential and random access to the data of the Multi Event Buffer
- The Chained readout allows to read one event from all the boards in a VME crate with a BLT access
- Optical Link
- Upgrade
Firmware can be upgraded via VMEbus or Optical Link
- Software
- General purpose C and LabView Libraries
- Demo and Software Tools for Windows and Linux
- Power Consumption
4 A @ +5 V
200 mA @ +12 V
200 mA @ -12 V
Compare
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- A654
- Cable assembly LEMO 00 male to MCX male – 1 m
- A659
- Cable assembly BNC male to MCX male – 1 m
- AI2700
- Optical Fiber Series
- A317
- Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm
- A318
- Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
- A4818
- USB 3.0 to CONET2 Adapter
- A316
- Cable assembly 2.54mm 2-pin header female - 5 cm
- A952
- Cable assembly 2.54mm 34 pin female to 2.54mm 34 pin female - 50 cm
- A953
- Cable assembly 2.54mm 34 pin female to two 2.54mm 34 pin female – 50 cm
- A954
- Cable assembly 2.54mm 34 pin female to two 2.54mm 16 pin female - 50 cm
Ordering Options
Code | Description |
---|---|
WVX1720EXAAA | VX1720E - 8 Ch. 12 bit 250 MS/s Digitizer: 1.25MS/ch, C20, SE RoHS |
WVX1720GXAAA | VX1720G - 8 Ch. 12 bit 250 MS/s Digitizer: 10MS/ch, C20, SE RoHS |