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DT5751

2/4 Channel 10 bit 2/1 GS/s Digitizer

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Overview

The CAEN Mod.DT5751 is a digitizer able to record waveforms along with performing advanced algorithms for online digital pulse processing (DPP) of charge integration and pulse shape discrimination with constant fraction timing and zero-length encoding.

Data is read by a Flash ADC, 10-bit resolution and 1 GS/s sampling rate (2 GS/s using half of the channels in DES mode*), which is well suited for fast signals as the ones coming from fast organic, inorganic and liquid scintillators coupled to PMTs or Silicon Photomultipliers, Diamond detectors and others. The acquisition can be channel independent and it is possible to make coincidence / anti-coincidence logic among different channels and external veto/gating. Multiple boards can be synchronized to build up complex systems.

In the case of DPP mode, data can be saved in time-stamped list mode to support higher input rates and improve the throughput performances.
Piled-up events can be rejected or saved for offline analysis. The acquisition in DPP mode is fully controlled by the CoMPASS software, which manages the algorithm parameters, builds, plots and saves the relevant energy, time, and PSD spectra. In the case of waveform recording mode, the user can take advantage of the CAENScope and WaveDump software to access and save the waveforms.

Libraries and demo software in C and LabView are available for integration and customization of specific acquisition systems.

The DT5751 comes in a Desktop form factor with 2/4 input channels (2 channels in case of DES mode*). The communication to and from the board is provided through USB and Optical Link interfaces.

(*) NOTE: DES mode is not available with DPP firmware.

Technical Specifications

GENERAL

Weight: 675 g
Form Factor: 154x50x164 mm3 (WxHxD) Desktop

ANALOG INPUT

Channels: 2/4 channels single-ended
Impedance: 50 Ω
Bandwidth: 500 MHz
Connector: MCX
Full-Scale Range: 1 Vpp (default); 0.2 Vpp (on request)
Offset: Programmable DAC for DC offset adjustment in the full range
Abs Max Rating: @1 Vpp: 3 Vpp (with Vrail max +3 V or –3 V for any DAC offset value)
@200 mVpp: 2 Vpp (with Vrail max +2 V or –2 V for any DAC offset value)

DIGITAL CONVERSION

Resolution: 10 bits
Sampling Rate:
1 GS/s (2 GS/s in DES mode)
Simultaneously on each channel
250 MS/s minimum by hardware down-sampling (see AN6308)

SYSTEM PERFORMANCES

ENOB: 9.04 (56 kS Buffer)
SINAD: 56.19 dB
THD: 70.2 dB
SFDR: 79.7 dB
SIGMA: 0.58 LSB rms (56 kS buffer, open input)

ADC CLOCK GENERATION
  • Clock source: internal/external
  • Onboard programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference
DIGITAL I/O
CLK-IN (AMP Modu II)
– AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by CAEN adapter)
– Jitter < 100 ppm requested
GPO (LEMO)
General purpose digital output
NIM/TTL, Rt = 50 Ω

GPI (LEMO)
General purpose digital input
NIM/TTL, Zin = 50 Ω
TRG-IN (LEMO)
External trigger digital input
NIM/TTL, Zin = 50 Ω
ACQUISITION MEMORY

1.835 MS/ch (1.9 ms @ 1GS/s) or 3.6 MS/ch in DES mode (1.9 ms @ 2GS/s); 14.4 MS/ch (15 ms @ 1 GS/s) or 28.8 MS/ch in DES mode (15 ms @ 2 GS/s) divisible into 1 ÷ 1024 buffers
Independent read and write access
Programmable event size and pre/post-trigger

TRIGGER
Trigger Source
– Self-trigger: channel over/under threshold for either Common or Individual (DPP only) trigger generation
– External-trigger: Common by TRG-IN connector
– Software-trigger: Common by software command

Trigger Propagation
GPO digital output
Trigger Time Stamp
– Waveform Recording: 31-bit counter, 16 ns resolution, 17 s range; 48-bit extension by firmware
– DPP-PSD: 48-bit counter, 1 ns resolution, 78 h range; 10-bit and 1 ps fine time stamp with digital CFD
– DPP-ZLEplus: 31-bit counter, 16 ns resolution, 17 s range; 48-bit extension by firmware
ADC & MEMORY CONTROLLER FPGA

Two Altera Cyclone EP3C16 (one FPGA serves 2 channels)

SYNCHRONIZATION
Clock Propagation
One-to-many: clock distribution from DT4700 to CLK-IN connector
Acquisition Synchronization
Sync Start/Stop through digital I/O (TRG-IN input, GPO output)
Trigger Time Stamp Alignment
By GPI input connector
COMMUNICATION INTERFACE

USB: USB 2.0 compliant Transfer rate up to 30 MB/s
Optical Link: CAEN CONET proprietary protocol, up to 80 MB/s transfer rate
Daisy chainable: it is possible to connect up to 8 ADC modules to a single Optical Link Controller (Mod.A2818/A3818/A4818)

FIRMWARE
Waveform Recording Firmware
Free firmware for waveform recording
Upgrades
Firmware can be upgraded via Optical Link or USB
DPP Firmware
Paid firmware for Digital Pulse Processing: DPP-PSD, and DPP-ZLEplus
SOFTWARE

Libraries: General-purpose C and LabVIEW Libraries
Configuration Tools: CAEN Upgrader for Firmware upgrade, Direct Register R/W, Example codes
Readout Software: CAEN WaveDump, CAENScope, CoMPASS, DPP-ZLEplus Demo software 

POWER CONSUMPTIONS

1.8 A @ 12 V (Typ.)

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Accessories

A654
Cable assembly LEMO 00 male to MCX male – 1 m
A659
Cable assembly BNC male to MCX male – 1 m
AI2700
Optical Fiber Series
A318
Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
A317
Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm
A4818
USB 3.0 to CONET2 Adapter
Digitizers Input Range Personalizations
Digitizers Input Range Customizations

Ordering Options

Code Description
WDT5751XAAAA DT5751 - 2/4 Ch. 10 bit 2/1 GS/s Digitizer: 3.6/1.8MS/ch, EP3C16, SE   RoHS

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