DT5742
16+1 Channel 12 bit 5 GS/s Switched Capacitor Digitizer
Features
- 12 bit @ 5 GS/s, Desktop module
- Switched Capacitor technology based on the DRS4 chip (designed at Paul Scherrer Institute)
- 1024 capacitor cells per channel (acquisition window of ~ 200 ns @ 5 GS/s)
- 5 GS/s, 2.5 GS/s, 1 GS/s, 750 MS/s software selectable sampling frequencies
- 16 analog input channels on MCX coaxial connectors
- 1 additional analog input (TR0):
- fast (low latency) trigger
- digitizable for high resolution timing (up to 50 ps)
- 1 Vpp input dynamic range (2 Vpp on request) with programmable DC offset adjustment
- Dead-time due to conversion: 110 µs (analog inputs only), 181 µs (TR0 input)
- Trigger modes:
- External on TRG-IN connector; common to all groups
- Fast (Low Latency) on TR0 connector; common to all groups
- Self-trigger, combinations of channels over-threshold in logic OR; common to all groups
- Memory buffer options: 128 events/ch; 1024 events/ch
- USB and Optical Link communication interfaces
- Demo software tools, C and LabVIEW libraries
Overview
The Mod. DT5742 is a Desktop module housing 16+1 Channel 12 bit 5 GS/s Switched Capacitor Digitizer. The input dynamic range is 1 Vpp on single-ended MCX coaxial connectors (16-bit DAC on each channel to control the DC Offset).
The digitizer is based on the Switched Capacitor Array DRS4 chip (Domino Ring Sampler). This technology relies on a series of 1024 capacitors (analog memory) in which the analog input signal is continuously sampled in a circular way.
The sampling frequency is 5 GHz by default and it can be programmed to 2.5 GHz, 1GHz, and 750 MHz. The analog to digital conversion is not simultaneous with the chip sampling phase, and it starts as soon as the trigger condition is met, thus producing a dead time of 110 μs in case only the analog inputs are digitized, 181 μs when also the fast trigger TR0 is digitized. When the trigger stops the DRS4 chip sampling (holding phase), the analog memory buffer is frozen, and the cell content is made available to the 12 bit ADC for the digital conversion.
The digital memory allows to store subsequent events, even if the readout is not yet started. Moreover, since the digital memory buffers work like FIFOs, the readout activity from USB or Optical Link does not affect write operations of subsequent events.
The available trigger sources are:
- External Trigger, trigger on TRG-IN connector, common to all enabled groups.
- Fast (Low Latency) Local Trigger, trigger on TR0 connector, common to all enabled groups. This mode is called “Fast” or “Low Latency” since the trigger latency to hold the DRS4 is reduced with respect to the external trigger. This trigger mode is convenient for high precision timing measurements, since the TR0 can be digitized and reported in the output data to be used as time reference.
- Self-trigger, common to all enabled groups. For each group is possible to select combination of channels (logic OR) that provide a trigger whenever the input crosses the threshold. This mode cannot be used at 5 GHz due to the trigger latency.
The module features the front panel CLK IN connector and an internal PLL for clock synthesis from internal/external references. The module is available with digital memory sizes of 128 event/ch or 1024 event/ch. DT5742 houses USB 2.0 and Optical Link interfaces. USB 2.0 allows data transfers up to 30 MB/s. The Optical Link supports transfer rate of 80 MB/s and offers Daisy chain capability. Therefore, it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod. A2818/A3818).
Software available (Windows and Linux): CAEN provides drivers for all the different types of physical communication channels, a set of C and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:
- CAENUpgrader: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.
Software for DT5742 running Waveform Recording Firmware:
- CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.
Technical Specifications
- GENERAL
Form Factor: Desktop
Weight: 690 g
Dimension: 166 W x 69 H x 171 D mm3
- ANALOG INPUT
Channels: 16 channels, special channel (TR0) Single ended
Bandwidth: 500 Mhz
Impedance: Zin = 50 Ohm
Absolute max analog input voltage: 3 Vpp (with Vrail max +3V or ‐3V) for any DAC offset
Connector: MCX
Full Scale Range (FSR): 1 Vpp
DC Offset: Programmable 16-bit DAC for DC offset adjustment on each channel. Range ± 1 V
- DIGITAL CONVERSION
Resolution: 12 bits
Switched Capacitor Array: Domino Ring Sampler chip (DRS4), 8+1 channels with 1024 storage cells each
Sampling Rate: 5 GS/s – 2.5 GS/s – 1 GS/s – 0.75 GS/s SW selectable, simultaneously on each channel
Dead Time (A/D Conversion): 110 μs, analog inputs only. 181 μs, digitizing TR0
- FPGA
Altera Cyclone EP3C16 (one FPGA manages 16+1 channels)
- TRIGGER
Trigger Source Trigger Propagation Trigger Time Stamp - Fast (Low Latency) trigger: Common trigger by programmable threshold on TR0
- Self‐trigger: Common trigger by combination of channels over/under threshold in logic OR ‐ External‐trigger: Common trigger by TRG IN connector
- Software‐trigger: Common trigger by software command
- GPO programmable digital output
- 30‐bit counter (extendable to 60‐bit by sw)
- 8.5 ns resolution
- 9 s range
- Timer reset by GPI
- ACQUISITION MEMORY
- 128 events/ch or 1024 events/ch Multi‐event buffer (1024 S/event, that is 200 ns/event @ 5 GS/s)
- Independent read and write access
- Programmable event size and pre/post‐trigger
- ADC Clock Generation
- Clock source: internal/external.
- On‐board programmable PLL provides generation of the main board clocks from internal (50 MHz local Oscillator) or external (front panel CLK‐IN connector) reference.
- DIGITAL I/O
CLK‐IN (AMP Modu II): GPO (LEMO) GPI (LEMO) AC coupled differential input clock
LVDS, ECL, PECL, LVPECL,
CML
(single ended NIM/TTL
available by A318 adapter)
Jitter < 100 ppm requestedTrigger digital output
NIM/TTL
Zin = 50 Ω
TRG‐IN (LEMO)
External trigger digital
input NIM/TTL
Signal Width: > 17 ns
Zin = 50 ΩSYNC/START
front panel digital input
NIM/TTL
Signal Width: > 17 ns
Zin = 50 Ω
- COMMUNICATION INTERFACES
Optical Link: CAEN CONET proprietary protocol, Up to 80 MB/s transfer rate, Daisy‐chain capability
USB: USB 2.0 compliant, Up to 30 MB/s transfer rate
- SYNCHRONIZATION
Clock Propagation: One‐to‐many: clock distribution from an external clock source to CLK‐IN connector
Acquisition Synchronization: Sync, Start/Stop through digital I/O (GPI or TRG‐IN input / GPO output)
Trigger Time Stamps Alignment: By GPI input connector
- CAEN FIRMWARE
Waveform Recording Firmware: Free firmware for waveform recording
Upgrades: Supported via USB/Optical Link
- SOFTWARE
Readout SW: WaveDump readout software with C source files and VS project for developers (Windows® , Linux®)
Libraries and Tools: General purpose C libraries with readout demos (Windows® , Linux® and LabVIEW™ support) and configuration tools
- ENVIRONMENTAL
Environment: Indoor use
Operating Temperature: 0◦C to +40◦C
Storage Temperature: –10◦C to +60◦C
Operating Humidity: 10% to 90% RH non condensing
Storage Humidity: 5% to 90% RH non condensing
Altitude: < 2000m
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: IPX0 Enclosure, not for wet location
- REGULATORY COMPLIANCE
EMC: CE 2014/30/EU Electromagnetic Compatibility
Directive Safety: CE 2014/35/EU Low Voltage Directive
- POWER REQUIREMENTS
1.7 A @ +12 V DC
AC‐DC 12 V/ 45 W power unit included
Compare
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- A654
- Cable assembly LEMO 00 male to MCX male – 1 m
- A659
- Cable assembly BNC male to MCX male – 1 m
- AI2700
- Optical Fiber Series
- A318
- Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
- A317
- Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm
- A4818
- USB 3.0 to CONET2 Adapter
- Digitizers Input Range Personalizations
- Digitizers Input Range Customizations
Ordering Options
Code | Description |
---|---|
WDT5742BXAAA | DT5742B - 16+1Ch. 12 bit 5 GS/s Switched-Capacitor Digitizer: 1024 events/ch (1kS/event), EP3C16,SE RoHS |
WDT5742XAAAA | DT5742 - 16+1 Ch. 12 bit 5 GS/s Switched-Capacitor Digitizer: 128 events/ch (1kS/event), EP3C16, SE RoHS |