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DT2730

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32 Channel 14 bit 500 MS/s Digitizer

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Features

  • 14-bit @ 500 MS/s ADC
  • 32 single-ended analog inputs on MCX connectors
  • 4Vpp input range with software selectable analog gain
  • VX2730 VME64x form factor also available
  • Open FPGA programming through graphical tool SCI-Compiler
  • Wide range of applications (from Neutrino Physics & Dark Matter to Nuclear and Particle Physics to Spectroscopic Imaging)
  • Suited for signals from Semiconductor Detectors coupled with CSPs (Si, HPGe) or scintillators coupled with PMTs (NaI, CsI)
  • On-board firmware selection for different acquisition modes:
    • Scope mode (simultaneous raw waveform acquisition on common trigger)
    • DPP-PSD mode (pulse shape discrimination and time acquisition on independent channel self-triggers)
    • DPP-PHAComing Soon mode (pulse height and time acquisition on independent channel self-triggers)
  • Multi-board synchronization and system building capabilities
  • Rack mount brackets included
  • Front panel fully programmable I/Os (4 LEMO TTL/NIM and 16 LVDS)
  • Special 125 MS/s 14bit DAC output (LEMO) for signal inspection, pulse generation, majority level
  • 2.5 GB of Total Acquisition memory (DDR4)
  • On-board Zynq® UltraScale +™ MPSoC integrating an Arm®-based CPU running Linux®
  • Multi Interface: USB-3.0 and 1/10 GbE
  • Fully supported by CoMPASS and WaveDump2 readout software
  • SDK for embedded Arm and host PC
More info
3 Years Warranty
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Overview

The CAEN Mod.DT2730 Digitizer is a 32-channel digital signal processor for radiation detectors in a Desktop form factor. It offers not only waveform digitization and recording but also Multi-Channel Analysis for nuclear spectroscopy using Silicon strip, segmented HPGe, Scintillation detector with PMTs, Wire Chambers, and others.

The DT2730 can perform pulse shape discrimination (PSD) and pulse height measurements (PHA Coming Soon), and other algorithms that will be gradually developed. Algorithm settings can be set independently channel by channel.

Each channel of the module digitizes the analog input, that can be the signal coming from a physics detector, with a 14 bit, 500 MS/s ADC. The sampled data are used to initiate the digital pulse processing sequence, managed in the FPGA at the firmware level. Different firmware types can be selected via software, according to the specific setup and acquisition mode.

  • Common trigger: all channels acquire simultaneously with a common trigger. The trigger can be fed externally or generated by a combination of individual channel discriminators. This mode is mainly intended for the acquisition of waveforms, like a digital oscilloscope. Options for zero suppression are available to remove not significant data.
  • Independent trigger: suited for trigger-less applications, where no global trigger is needed but each channel acquires waveforms upon its self-trigger which fires through a digital discriminator, independently of the others.
  • DPP: real-time processing in the FPGA allows for the extraction of physical parameters from the waveform (e.g. pulse height, charge, timestamp, PSD), well suited for high counting rate applications. It is yet possible to save both raw waves and parameters.

A template of the firmware is available for customers who want to personalize the acquisition to implement custom algorithms for pulse processing in the open FPGA. The user can have control of the data output information and customize the trigger logic to get several combinations of self-triggers and I/O signals to validate or discard the events.
Custom software can run on the onboard CPU for data reduction and analysis. Multi-board synchronization can be implemented via backplane or front panel easy-cabling options.
The communication interface selection offers fast readout options: USB 3.0 type-C and 1/10 Gigabit Ethernet.

For detailed information on available firmware for the 2730 family and the structure of programming files (.CUP), please refer to the following page.

Supported third-party software:

Technical Specifications

GENERAL

Weight: 3120 g
Form Factor: Desktop | Desktop Rack
Dimension: Desktop: 338 W x 100 H x 283 L mm³ (without connectors) | 338 W x 100 H x 295 L mm³ (including connectors). Desktop-Rack: 19” rack mount

ANALOG INPUT

Channels: 32 channels, single-ended
Bandwidth (-3dB): 250 MHz guaranteed for Gain ≥ 2
Impedance: 50 Ω
Gain: x1 ÷ x20, software programmable in steps of 1dB independently on each channel
Connector Type: MCX
Full Scale Range: 4 Vpp ÷ 0.2 Vpp
DC Offset: Adjustable in the ± 2.5V range independently on each channel

DIGITAL CONVERSION

Resolution: 14 bits
Sampling Rate: 500 MS/s (simultaneously on each channel)

SYSTEM PERFORMANCE

ENOB (Typ.): 10.5 (@50MHz, -3dB, Gain x2)
RMS (Typ.): 2.4 LSB RMS (@Gain x2)

DIGITAL I/O
CLK-IN (CLK-OUT)

  • Two differential pairs:
    • CLK, reference clock signal
    • SYNC, synchronization signal (start/stop, T0, etc.)
  • 2.54mm 4-pin AMPMODU Mod II male connector
  • CLK-IN: AC-coupled LVDS, ECL, PECL, LVPECL, CML (Zdiff = 100 Ω)
  • CLK-OUT: LVDS
  • Daisy chainable for multiboard synchronization with sw programmable CLK-OUT delay shift
 LVDS I/O

  • 16 differential pairs
  • Sw programmable I/O function (individual self-trigger outputs, trigger validations, Veto, Busy, Start, Stop, Pattern Input, etc.)
  • LVDS
  • Zdiff = 100 Ω (when set as inputs)
  • 2.54mm 34-pin AMPMODU Mod II male connector
 TRG-IN/TRG-OUT/GPIO/S-IN

  • General-purpose digital I/Os
  • Sigle-ended TTL/NIM
  • LEMO 00 male connector
  • Sw programmable function (trigger, veto, busy, etc.)
  • TRG-IN/S-IN: internally terminated with 50 Ω (Zin = 50 Ω)
  • TRG-OUT requires Rt = 50 Ω
  • GPIO as Input must be terminated with 50 Ω
  • GPIO as TTL Output requires Rt = 50 Ω
  • GPIO as NIM Output requires Rt = 50 Ω or 25 Ω
DAC OUT
  • DAC output for signal inspection, pulse generation, majority level
  • ±1 V @ 50Ω load
  • ±2 V @ hi-Z load Output Range
  • 14-bit Digital-to-Analog Converter (DAC)
  • LEMO 00 connector
ACQUISITION MEMORY

5 GB total DDR4 memory size (83.886 MS/ch) divisible in multiple buffers
Maximum record length: 84 ms @ 500 MS/s (total memory size divided by 2)1

1 Value referred to the Scope firmware (minimum of two buffers admitted)

COMMUNICATION INTERFACES
1 GbE

  • Copper RJ45 or optical LC connector on SFP+ transceiver
  • Protocol: TCP
  • Transfer rate: 110 MB/s

 

10 GbE (*)

  • Copper RJ45 or LC optical connector on SFP+ transceiver
  • Transfer rate: 850 MB/s

* Contact CAEN Support

  

USB 3.0

  • USB-C type connector
  • Protocol: USB 3.1 GEN1
  • Transfer rate: 280 MB/s
TRIGGER
Trigger Modes

  • Common: all channels acquire simultaneously with the trigger (software, external or logic combination of self-triggers)
  • Individual: each channel acquires independently with its self-trigger
  • Correlated: the individual self-trigger of each channel is validated by the coincidence/anticoincidence logic between other self-triggers and/or external I/Os
 Trigger Timestamp – Scope firmware

  • Resolution: 8 ns coarse timestamp
  • Counter range: 48 bits
  • Full-scale range: ~625 h
 Trigger Time Stamp (DPP firmware)

  • Resolution: 2 ns coarse timestamp, 2 ps fine timestamp
  • Counter range: 48 bits
  • Full-scale range: ~156 h
SYNCHRONIZATION
  • Clock Propagation
    Typical 62.5MHz frequency optionally distributed:
    • By fan-out to CLK-IN
    • By CLK-IN/CLK-OUT daisy chain with sw programmable CLK-OUT delay shift
    Custom frequencies can be supported on request
  • Acquisition Start/Stop: Daisy chain or fan-out propagation through CLK-IN/CLK-OUT or NIM/TTL, LVDS I/O
  • Data Sync: Busy/Veto logic on LVDS I/Os or NIM/TTL I/Os for event building synchronization
  • Trigger Time Stamp: Reset Software from START run command or Hardware from S-IN/GPIO input (Scope Firmware only)
  • Trigger Distribution: TRG-IN/TRG-OUT NIM/TTL LEMO I/Os (common trigger) or LVDS I/Os (common or individual trigger)
FPGA

Xilinx Zynq UltraScale+ Multiprocessor System-on-Chip mod. XCZU19EG
Processing System based on Quad-core Arm with 2GB DDR4 memory @2400 MT/s (Linux OS onboard)
Programmable logic with more than 1100K system logic cells and 80Mbit memory

CAEN FIRMWARE

Developed by CAEN, stored in the on-board FLASH memory, and live rebootable by Web Interface

DPP Firmware

Firmware implementing Digital Pulse Processing algorithms:

  • DPP-PSD: Pulse Shape Discrimination
  • DPP-PHA: Pulse Height Analysis (Coming Soon) 
 Scope Firmware

Firmware for the waveform recording

 Upgrades

CAEN firmware can be uploaded via Web Interface (scope and DPP firmware, and their updates)
USER FIRMWARE (OPEN FPGA)
Scope Personalization

Customizable features of the Scope firmware:

  • Common trigger
  • Simultaneous waveform recording on 32 channels management
  • Trigger logic
  • Wave processing
 DPP Personalization

Customizable features of the DPP firmware:

  • Individual trigger and channel acquisition management
  • DPP algorithm
  • Trigger logic
  • Event data information
 SCI-Compiler

User Firmware Generator and Compiler Graphical Tool for CAEN Programmable Boards
FPGA
  • Xilinx Zynq UltraScale+ Multiprocessor System-on-Chip mod. XCZU19EG
  • Processing System based on Quad-core Arm with 2GB DDR4 memory @2400 MT/s (Linux OS onboard)
  • Programmable logic with more than 1100K system logic cells and 80Mbit memory
SOFTWARE
Readout SW

  • CoMPASS spectroscopy software (for DPP firmware only)
  • WaveDump2 (for Scope firmware only)
  • SCI-Compiler (Open FPGA) Automatic generation of drivers (USB, ethernet), libraries, and demo software for Windows®, Linux®
 SDK and Tools
General purpose C libraries with demo samples for host Windows® and Linux® PC, and embedded Arm processor		 Web Interface
Firmware management (e,g. upgrades and on-the-fly selection of the firmware to run), board information, PLL and Ethernet configuration, board status monitoring, DPP license management

 

 

ENVIRONMENTAL

Environmental: Indoor use
Operating Temperature: 0°C ÷ +40°C
Storage Temperature: -10°C ÷ +60°C
Operating Humidity: 10% ÷ 90% RH non condensing
Storage Humidity: 5% ÷ 90% RH non condensing
Pollution Degree: 2
Overvoltage Category: II
EMC Environment: Commercial and light industrial
IP Degree: Enclosure (desktop models), not for wet location

REGULATORY COMPLIANCE

EMC: CE 2014/30/EU Electromagnetic compatibility Directive
Safety: CE 2014/35/EU Low Voltage Directive

POWER REQUIREMENTS

Mains-powered (130 Watt @110V/220V).

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Accessories

A319A
Clock & Sync cable assembly for Digitizer Series 2.0 - 20 cm
A319B
Clock cable assembly from Digitizer Series 1.0 to Digitizer Series 2.0 - 20cm
A316
Cable assembly 2.54mm 2-pin header female - 5 cm
A952
Cable assembly 2.54mm 34 pin female to 2.54mm 34 pin female - 50 cm
A953
Cable assembly 2.54mm 34 pin female to two 2.54mm 34 pin female – 50 cm
A954
Cable assembly 2.54mm 34 pin female to two 2.54mm 16 pin female - 50 cm

Ordering Options

Code Description
WDT2730XAAAA DT2730 - 32 Ch. 14 bit 500MS/s Digitizer with Programmable Input Gain    RoHS

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