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FERS-5200

Front-End Readout System

  • Platform for the readout of large arrays of detectors (SiPM, MA-PMTs, Gas Tubes, Si detectors, …)
  • Based on a complete family of Front-End cards (FERS units) + Concentrator Board
  • Scalability: from a single standalone FERS unit for prototyping to many thousands of channels, with simple tree network structure.
  • Flexibility: FERS units can be tailored to specific detectors and applications
  • A5202 Front-End unit for SiPM readout with Weeroc CITIROC chip
  • Modularity: multiple FERS units can be managed via a single Concentrator board  DT5215 (max. 8192 channels for A5202)
  • Concentrator Board: multiple Concentrator Boards can be synchronized to build extremely large readout systems
  • Compact size: high-channel density FERS units are very efficient in terms of detector connectivity and footprint
  • Easy-Sync: a single optical link (TDlink) for data readout, slow control and boards synchronization
  • Acquisition modes: spectroscopy (PHA), counting, time stamping, waveform recording, depending on the Front-End ASIC
  • Data Management: Concentrator Board DT5215 manages event building, processing and formatting
  • Form Factor: FERS unit available in boxed version for desktop use or naked for integration into mechanical frames

Overview

FERS-5200 is a Front-End Readout System designed for large detector arrays, such as SiPMs, multi-anode PMTs, Silicon Strip detectors, Wire Chambers, GEM, Gas Tubes and others.

FERS is a highly-scalable distributed platform. Each unit is a small card which houses 32 or 64 channels and includes Front End electronics, A/D converters, trigger logic, synchronization, local memory and readout interface.

FERS was designed with flexibility in mind: a single user-interface and readout infrastructure has been designed to support and perform a wide range of front-end tasks suitable for a large variety of detector types.  In most cases, the front-end is based on ASIC chips. This design is perfect for large detector arrays, combining high density, cost-effective integration of multi-channel readout electronics with a small footprint and low power draw.  The Front End ASIC can implement an analog chain made of preamplifier, shaper, peak sensing and discriminator: this is the case of the model A5202, based on the Citiroc-1A chip produced by Weeroc for SiPM readout. In other cases, the ASIC is a fast flash ADC (1 GS/s or more) that records the waveform of the input pulses and makes it possible to apply digital algorithms providing timing, energy and pulse shape information.

A5202 - DT5202

For prototyping and R&D, all that is required is a single standalone FERS Unit connected to a computer via USB 2.0 or Ethernet 10/100T.  This offers a low cost, easy-to-use option to evaluate the system and the ASIC chip housed in the FERS unit.  When the solution is validated, it becomes extremely quick and easy to scale up by way of connecting multiple FERS unit to a Concentrator board via optical TDlink.  TDlink is the critical physical connection that guarantees high throughput data readout, accurate timing synchronization, and slow control.

Immagine esplicativa
Immagine esplicativa

DT5215

One DT5215 (FERS Data Concentrator) can manage up to 8 TDlinks. Each TDLink can connect and manage up to 16 FERS units in daisy chain. In the case of the A5202 (CITIROC 1A), it makes 8192 channels read out by a single Concentrator. Multiple concentrator boards can be synchronized to further extend the total number of channels. The Data Concentrator is connected to the Host computer through 1/10 Gb Ethernet or USB 3.0.

A Linux-based Single Board Computer is embedded in the Concentrator board. It manages the data readout from the network of FERS units and the event data building according to the time stamp and/or trigger ID of the event fragments acquired by each unit. Sorted and merged data packets are then stored to the local memory and finally sent to the host computers through a fast 10 GbE or USB 3.0 link. Custom algorithms for data processing and reduction can be easily uploaded by the user onto the embedded CPU.

 

One computer, one Concentrator, thousands of channels

FERS-5200 is an extendable system: the same FERS unit can be used as stand-alone system for prototyping and validation, and then added to a greater network tree for the readout of large arrays. This strategy eliminates waste and maximizes cost efficiency.

The core of the scalability of the FERS-5200 is the optical TDlink, which manages simultaneously data stream, unit synchronization and slow control.

The concentrator board DT5215 hosts 8 optical links, each capable of sustaining up to 16 FERS units in daisy chain. In the case of A5202 for SiPM readout, this means 8192 channels managed by a single Concentrator board… and multiple Concentrator board can be synchronized to support a limitless number of channels!

 

Models

Interfaces & I/O

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Software

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Request info

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Brochure

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