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DT5203

Coming Soon

Desktop 64 Channel picoTDC unit for FERS-5200

Features

  • 64-ch TDC unit for high-resolution timing applications housing the CERN picoTDC
  • Part of FERS-5200, the CAEN platform for the readout of large arrays of detectors (SiPM, MA-PMTs, Gas Tubes, Si detectors, …)
  • Timing resolution: LSB = 3.125 ps, RMS typ. ~ 7ps
  • LVDS-compliant input, possibility to use single-ended analog/NIM/TTL through dedicated adapters
  • Acquisition of rising/falling edge timestamps enabling ToA and ToT measurements
  • Scalability and easy-synch: up to 128 cards (8192 channels) can be managed and synchronized by a single DT5215 Concentrator Board, thanks to the optical TDLink
  • Janus software available for board and DAQ control
  • Flexibility: a full range of adapters and cables for different kind of applications and sensors remotization
  • Naked unit available (A5203) for customizable mechanical frames

 

Overview

FERS-5200 is a front‐end readout system designed for the readout of large detector arrays, such as SiPMs, multi‐anode PMTs, Silicon Strip detectors, Wire Chambers, GEMs, Gas Tubes and others. FERS‐5200 is a distributed and scalable system, where each unit is a small card that houses 64 or 128 channels. It features a detector specific Front-End interfaced to a common infrastructure that guarantees readout interfaces, slow control and synchronization. Typically, the front-end is based on ASIC chips that allow for high density, cost effective integration of multi-channel readout electronics into small size and low power modules. FERS is a flexible platform: combining the same back-end (i.e. readout architecture and interface) with different types of front-end to fit a wide range of detectors.

The DT5203 (and A5203, which is the naked version for use in custom mechanical frames) is a member of the FERS-5200 family. It uses the picoTDC chip (produced by CERN) for high-resolution multi-hit time measurements.

Each readout channel accepts LVDS signals and measures the time stamp of both rising and falling edges with an LSB of 3.125 ps. In this way, the unit is able to reconstruct Time of Arrival of signals as an absolute timestamp or as a deltaT with respect to a common Tref pulse. The picoTDC can also acquire Time over Threshold information and combine it with the edge time stamp. The ToT allows for amplitude estimation, energy spectrum reconstruction, and timing walk correction, and it also enables the possibility to achieve optimal timing resolution with no need of Constant Fraction Discriminators.

For small setups a single A5203 unit can be used stand alone, without any additional hardware, by simply connecting the unit to a PC via USB 2.0 or Ethernet 10/100T. For large readout systems, a flexible and scalable network of units can be created by means of the high speed optical link called TDlink.  The TDlink system supports up to 128 FERS units to be connected to and managed by one DT5215 FERS Data Concentrator Module. The TDlink supports optical daisy chaining and provides slow control, high speed data readout, synchronization between the units (clock and sync distribution), as well as command broadcasting for triggers, time resets, etc

The A5203 is fully supported by the CAEN Janus open source software for Windows® and Linux. Janus can run in console mode (C program, without graphics) or connected to a GUI written in Python. The GUI has configuration panels and run control which make it easy to manage acquisition. Both console and GUI modes acquire data from multiple boards, manage the event building and timing histograms (deltaT and/or ToT), display data statistics (hit rate, throughput, etc…), plot histograms, and save output, including spectra and list files with the acquired timing data.

The A5203 supports the following acquisition modes:

  • Common Start: channel 0 is the common start that opens the acquisition gate and represents the time reference. All other channels provide deltaT time measurements: DTN = TN – T0. The gate width is programmable by software. Any hit falling outside the gate will be discarded. In the case of multiple hits in the same channel only the first will be used for the deltaT acquisition (although all multiple hits will be acquired by the picoTDC). The common time reference on channel 0 can be driven from the relevant LVDS input or from the T0, T1 IN/OUT connectors (NIM or TTL), enabling the possibility to distribute the Tref signal among multiple boards through a daisy-chain. In Common Start mode the event data are composed by the Trigger ID, the 56 bit coarse time stamp (LSB = 12.8 ns) for the absolute time, the Tref (i.e. Ch 0) fine time stamp (LSB = 3.125 ps) and the list of the deltaT (LSB = 3.125 ps) for the channels from 1  to 63 (only those channels that have been hit). If enabled, ToT is also acquired for all channels, including Ch0 (Tref)
  • Common Stop: similar to common start, but the common time reference on channel 0 is used as a stop that closes the acquisition gate: DTN = T0 – TN. In case of multiple hits only the last one will be used.
  • Trigger Matching: in this mode there is a trigger signal (typically coming from the T0/T1 inputs) which defines an acquisition window with programmable width and offset. All hits falling within that window will be recorded. Multi-hit acquisition is supported. All time measurements are referred to the start of the acquisition window with coarse timing resolution (LSB = 25.6 ns).  However, the relative timing between the channels keeps the maximum resolution of 3.125 ps. In Trigger Matching mode the event data are composed by the Trigger ID, the 56 bit coarse time stamp (LSB = 12.8 ns) for the absolute time of the trigger, and the list of the hit time stamps of all channels (LSB = 3.125 ps). It is possible to save leading edge only, leading edge and trailing edge, or leading edge + ToT.
  • Streaming: this acquisition mode implements a continuous hit recording, without any gate or trigger windowing. All hits received by the inputs are converted into a 64 bit time stamp (LSB = 3.125 ps) and saved in the form of a sorted list. It is possible to save leading edge only, leading edge plus trailing edge, or leading edge plus ToT. In order to make the data management easier the list is split into time frames of fixed width, thus creating event data packets identified by an ID and a coarse time stamp.

 

FULL RANGE OF ACCESSORIES FOR SENSORS REMOTIZATION!

The DT5203 offers four 17 x 2, 2.54 mm pin header connectors (A5255 adapter included) to allow for easy-use of standard flat cables.

 

Moreover, the A5255 panel adapter can be removed to expose an input edge card connectors type HSEC8170, mating to a Samtec HSEC817001SDV. The connector has 140 contacts (0.8 mm pitch) and brings 64 LVDS pairs, a few control signals and a 3.3V power line. The edge connector makes it possible to build a custom backplane or a flange for the interconnection to the detectors.

A wide range of adapters and cables has been also specifically designed for FERS-5200 boards, in order to provide versatility of choice and the ability to remotely operate the detectors:

  • A5255, four 17×2, 2.54 mm pin header adapter (64 channels in total) for flat cables. Aux LEMO connector for NIM/TTL signals, driving channel 0, that is the common time reference (selection between NIM/TTL or LVDS of ch0 via solder jumpers).
  • A5256, 16+1 channel dual threshold, leading edge discriminator for analog single-ended signals on LEMO coaxial connectors. It includes ultra-fast comparators with programmable thresholds (DAC) and accepts both positive and negative analog pulses as well as NIM or TTL logic signals. Dedicated connector for Channel 0 (Tref). The dual threshold allows for a better ToT to amplitude conversion and walk correction, as well as pulse shape discrimination.

  • A5260, the remotization cable for FERS-5200 board.

A detailed documentation of all FERS-5200 header adapters and cables is available on CAEN website.

 

Technical Specifications

MECHANICAL

Dimensions                                                   Weight

106.1 W x 56.1 H x 186.8 L mm3                     503 g

(including A5255 pins)

TDC INPUT

64 channels (four 17 x 2, 2.54 mm pin header pins)

Removable panel to expose 1 edge connector type HSEC8-170 – Mating connector: Samtec HSEC8-170-01-S-DV

Input Type:              LVDS
Input voltage:          Min = -40 mV           Max = +1500 mV
Common Mode:      Min = +70 mV          Max = +1200 mV
Differential voltage: Min = +140 mV        Max = +450 mV
Input Termination:  100 Ω

INPUT ADAPTERS

A5255: 4 x 34 contacts, 1.27 mm picth ribbon cables (i.e. 4 x 17×2 2.54 mm Headers). Aux LEMO input (NIM/TTL, 50Ω) for alternative driving of channel 0.

A5256: 32+1 channel discriminator. Analog inputs on MCX, 50Ω, positive or negative. SW programmable individual threshold (-0.5V to +0.5V, 14 bit DACs). COOMING SOON.

A5260: micro-coaxial remotization cable

By default, the desktop version DT5203 comes with an A5255 as a front panel.

TIMING RESOLUTION

LSB = 3.125 ps

delta TRMS = ~7 ps. Tested with pulse generator (1 Vpp, 0.8 ns rise/fall), passive splitter and 5 ns cable delay
delta TRMS = ~20 ps with variable amplitude pulses (30 mV to 1 V) and walk correction by ToT

DYNAMIC RANGE

Time measurement dynamic range in picoTDC:
– Leading Edge only:              TLEAD = 26 bits (FSR = ~210 us)
– Leading + Trailing Edge:      TLEAD / TTRAIL = 26 bits (FSR = ~210 us)
– Leading + ToT8:                   TLEAD = 19 bits, TTOT = 8 bits (LSB size and FSR can be programmed)
– Leading + ToT11:                 TLEAD = 16 bits, TTOT = 11 bits (LSB size and FSR can be programmed)

Coarse time stamp in FPGA (56 bits @ 12.6 ns) con be combined with picoTDC data to extend the full scale range of the time measurement to almost any value

FRONT PANEL I/Os

T0-IN, T1-IN:           LEMO-00 connector, NIM or TTL (terminated to 50 Ω)
T0-OUT, T1-OUT:  LEMO-00 connector, TTL (50 Ω termination required)
Jumpers for IN-OUT bypass and termination removal (daisy chaining)

Functions (SW programmable):
Trigger, Acquisition Start/Stop, Sync, Busy, Veto, Signal inspection, etc…
T0/T1 inputs can be used to drive TDC-Ch0 = Tref (possible degradation of the resolution (t.b.d.)

FRONT PANEL LEDs

GREEN: Power-ON, Init-Done, Run, Trigger, Data Ready, T0-IN, T1-IN
ORANGE: Event Overrun (rejected triggers because received while busy)
RED: Failure (missing clock, over-temperature, etc…)

INTERNAL PULSER

Fast LVDS output with programmable frequency and width, for debug purposes

ACQUISITION MODES

Common Start:
TDC ch. 0 is the common start that opens the acquisition gate and represents the time reference. All other channels provide deltaT time measurements: delta_TN = TN – T0. The gate width is programmable by software. Any hit falling outside the gate will be discarded.
Output Data: delta_T or delta_T+ToT

Common Stop:
Same as common start, but ch. 0 is used as a common stop that closes the acquisition gate: delta_TN = T0 – TN.

Trigger Matching:
The trigger signal (typ. from T0/T1 inputs) defines an acquisition window with programmable width and offset. All hits falling into the window will be recorded. Multi-hit acquisition is supported. All time measurements are referred to the Coarse Trigger Time Stamp (LSB = 25.6 ns), while the relative time between the hits keeps the maximum timing resolution (LSB = 3.125 ps).
Output Data: TLEAD or TLEAD+TTRAIL or TLEAD+ToT

Streaming:
continuous hit recording, without any gate or trigger windowing. All hit time measurements are expressed as 64 bit time stamps (LSB = 3.125 ps) and saved in the form of a sorted list.
Output Data: TLEAD or TLEAD+TTRAIL or TLEAD+ToT

COMMUNICATION INTERFACES

USB 2.0: microUSB connector. Bandwidth = ~ 3 MB/s
Ethernet: RJ-45, 10/100 Mbit/s.  Bandwidth = ~ 2 MB/s
TDlink: Optical link (~60 MB/s) with synch distribution. Allows for multi-board synchronization, slow control and data readout- Data Concentrator DT5215 required.

POWER REQUIREMENTS

power supply voltage:             +12 V (min = +7V, max = +15V)
power consumption:                700 mA @ +12V (8.4 W)

110V/220V AC/DC converter provided with DT5203

FIRMWARE

Firmware of FPGA be upgraded via USB or Ethernet
Firmware of µC can be upgraded via Ethernet only

SOFTWARE

Janus: open source software for Windows® and Linux. Two operating modes:
– console mode: C program with console commands and display (gnuplot for plots). Scriptable execution.
– GUI mode: Python GUI for configuration and run control (C program running in background).

Janus highlights:
– Multiple board acquisition with event building based on trigger ID or time stamp;
– Histograms (spectra): delta_T start-stop, ToT, delta_T between hits on the same channel;
– Energy spectrum reconstruction and delta_T walk correction by ToT with user defined linearization curves;
– Live Display: channel hit count and rate, trigger rate, lost triggers, data throughput, acq. time, etc…;
– Plots: DT, ToT, hit rate, 2-D heat map with channel hit rates;
– Output Files: histograms (time spectra), list files (TLEAD, TTRAIL, ToT, delta_T), Run Info, Sync file.

DT5203

Desktop 64 Channel picoTDC unit for FERS-5200
Product page
DT5203
  • Documentation
  • Software
  • Firmware

Data Sheet

Name File extension File size Revision Last update
A5203/DT5203 - 64/128 Channel picoTDC unit for FERS-5200 PDF 496.26 kB 1 April 5th, 2022

Readme:  

Build:
License  

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Accessories

A5260
Remotization cable for FERS-5200 boards

Ordering Options

Code Description
WDT5203BXAAA DT5203B – Desktop 128 channel pico-TDC unit for FERS  RoHS
WDT5203XAAAA DT5203 - Desktop 64 Channel pico-TDC unit for FERS-5200  RoHS

Contacts

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