DT5202
Desktop 64 Channel Citiroc unit for FERS-5200
Features
- Front-End unit for SiPM readout housing 2 Weeroc Citiroc-1A chips
- Part of FERS-5200, the CAEN platform for the readout of large arrays of detectors (SiPM, MA-PMTs, Gas Tubes, Si detectors, …)
- Onboard A7585D SiPM power supply
- Acquisition modes: Spectroscopy (PHA), Counting, Timing with ToT
- Boxed FERS unit (DT5202) for desktop use or naked (A5202) for customizable mechanical frames
- Up to 128 DT5202 units can be managed by a single DT5215 Concentrator Board, i.e. up to 8192 SiPM pixels
- Flexibility: a full range of accessories for sensors remotization
- Scalability: from a single standalone FERS unit for prototyping to many thousands of channels, with simple tree network structure
- Modularity: multiple FERS units can be distributed on large detector volume and managed by a DT5215 Concentrator board
- Compactness: front-end cards with high channel density ASICs and effective connection to the detector backplane
- Easy-synch: one single optical link (TDlink) for data readout, slow control and boards synchronization via DT5215 Concentrator Board
Overview
FERS-5200 is a front‐end readout system designed for the readout of large detector arrays, such as SiPMs, multi‐anode PMTs, Silicon Strip detectors, Wire Chambers, GEMs, Gas Tubes and others. FERS‐5200 is a distributed and scalable system, where each unit is a small card that houses 64 or 128 channels with preamplifier, shaper, discriminator, ADC, trigger logic, synchronization, local memory and readout interface. In most cases, the front‐end is based on ASIC chips that allow for high density, cost effective integration of multi‐channel readout electronics into small size and low power modules.
The first FERS‐5200 unit being developed is the A5202 (DT5202 is the boxed version for desktop use) that uses the Citiroc‐1A chip produced by WeeROC for SiPM readout. More precisely, the DT5202 houses two Citiroc‐1A chips (64 readout channels). Each readout channel is composed of a Preamplifier, a Slow Shaper with peak sensing detector and a Fast Shaper followed by a discriminator. Peak sensing values from each Citiroc‐1A are converted sequentially (multiplexed output) by an ADC. The 64 channel self‐triggers (discriminator outputs) can be used for counting, time stamping, to determine the Time over Threshold (ToT) information and also to generate the board bunch trigger that starts the A/D conversion. The DT5202 board is also provided with the A7585D power supply module for biasing the SiPMs and the interfaces for readout, synchronization and control.
The most relevant DT5202 acquisition modes are:
- Spectroscopy Mode: This mode (also indicated as Pulse Height Analysis, PHA) works with a global (bunch) trigger, either coming from an external source or generated by a combination of the channel self‐triggers. As soon as a trigger is issued, all channels start simultaneously the A/D conversion of the pulse amplitude.
- Counting Mode: In this mode, the self‐triggers of each channel are individually counted, with the counting intervals defined by an internal periodic gate with programmable width or by an external signal.
- Timing Mode: This mode generates a list of individual time stamps (referred to a Time Reference signal) optionally combined with the Time over Threshold (ToT) information that gives a rough estimation of the pulse amplitude.
One DT5202 unit can be used stand alone, without any additional hardware, just connected to the PC via USB 2.0 or Ethernet 10/100T.
For large readout systems, a flexible and scalable network of units can be created by means of the high speed optical link called TDlink that allows up to 16 FERS‐5200 units to be connected in daisy chain (ring) providing data readout, synchronization between the units and broadcasting of commands (e.g. triggers, time resets, etc.). The DT5215 is a data collector board (FERS‐CB) housing 8 TDlink masters that will make it possible to manage up to 128 FERS‐5200 units.
The DT5202 is fully supported by the CAEN Janus software on Windows®. The Janus software release for Linux is COMING SOON.
A FULL RANGE OF ACCESSORIES FOR SENSORS REMOTIZATION!
A wide range of adapters and cables has been also specifically designed for FERS-5200 boards, in order to provide versatility of choice and the ability to remotely operate the detectors:
- A5250, the 2.54 mm pin header adapter for FERS-5200 boards (included in the DT5202 kit)
- A5251, the Hamamatsu MPPC header adapter for A5202/DT5202 boards
- A5253, the 3-pin header adapter for FERS-5200 boards
- A5254, the OnSemi (ex SensL) MPPC header adapter for A5202/DT5202 boards
- A5255, Quad 17×4 Header Adapter
- A5260, the remotization cable for FERS-5200 boards
- A5261, the SiPM remotization cable coupling to the A5253 adapter
A detailed documentation of all FERS-5200 header adapters can be found here.
Technical Specifications
- MECHANICAL
Dimensions 106.1 W x 56.1 H x 186.8 L mm3
(including A5250 pins)
Weight 503 g
- INPUTS
64 channels (= 2 Citiroc-1A chips)
- SIGNAL POLARITY
Positive
- SENSITIVITY
Dual range: Low Gain (LG)/High Gain (HG). Channel-by-channel individual setting of the gain value through a CSP feedback capacitor, Cf, adjustable from 25 fF to 1575 fF (25 fF step):
- LG = 1.5 pF/Cf (max gain = 60)
- HG = 10 x LG = 15 pF/Cf (max gain = 600)
- DYNAMIC RANGE
The Citiroc-1A Preamplifiers ensure a dynamic range from 160 fC to 400 pC (i.e. from 1 to 2500 photo-electrons with 106 SiPM gain)
- SHAPING TIME
Slow Shaper 7 options from 12.5 ns to 87.5 ns
(12.5 ns step)
Fast Shaper Fixed: 15 ns
- FRONT PANEL I/Os
4 general purpose programmable LEMO I/Os connectors available:
- 2 (T0-IN and T1-IN) to be used as input (LVTTL and NIM)
- 2 (T0-OUT and T1-OUT) to be used as output (LVTTL)The T1-IN and T0-IN connectors are 50 Ω terminated with a jumper.
The jumper can be moved to perform a bridged connection for daisy chain trigger distribution or wired-OR in a multi-board system.
- DIGITAL PROBE
LVTTL signal with different functions can be transmitted via the front panel output connectors.
- ANALOG PROBE
SMA connectors allowing the user to acquire analog signals from a specific, software selectable stage of each Citiroc-1A signal shaping chain:
- LG/HG Preamplifier output
- LG/HG Slow Shaper output
- Fast Shaper output
- SELF-TRIGGERS
- Programmable 10-bit DAC for common threshold
- Minimum threshold: 1/3 photo-electron
- Separate trigger line per channel
- Programmable 4-bit DAC for channel-by-channel threshold fine adjustment
- Logic combination (AND, OR, Majority) of triggers for start of A/D conversion and time reference.
- EXTERNAL TRIGGERS
From TDlink, T1-IN or T0-IN. T0/T1 lines can be daisy chained (IN-OUT) or wired-OR (bidirectional) to share a common global trigger between multiple units.
- HIGH VOLTAGE POWER SUPPLY
Single channel PCB mounted A7585D High Voltage Power Supply:
- Common SiPM bias voltage: 20 ÷ 85 V
- Settling precision: ± 20 mV
- Individual channel adjustment: 8-bit (2.5V or 4.5V dynamic range)
- Max. output bias current: 10 mA (software programmable limit)
- Programmable temperature compensation
- ACQUISITION MODES
Spectroscopy Mode (PHA)
- Simultaneous acquisition of all channels
- 13-bit A/D conversion
- Systematic conversion time ~ 10 µs (Max. trigger rate ~ 100 kHz)
- Independent digital thresholds for channel-by-channel zero suppression (ZS)
Counting Mode
- Channel-by-channel independent counting
- Common trigger to define counting window (Dwell time)
- Maximum counting rate (per channel): ~ 20 Mcps
Timing Mode
- Independent channels (merged list, time sorted)
- 0.5 LSB resolution (~ 250 ps RMS)
- Time stamp referred to a common time reference coming from T0-IN/T1-IN connectors or from the logic combination of channel self-triggers
- Spectroscopy information (lower resolution) from Time over Threshold (ToT) information
- TIME STAMP
- 56-bit counter, 8 ns step
- Up to 128 boards can be synchronized with the DT5215 FERS-CB by sending a time stamp reset signal via TDlink (COMING SOON)
- COMMUNICATION INTERFACES
- USB: USB2.0 connector, type microUSB-B
- Ethernet: Ethernet connector, type RJ-45. Supports 10/100 Mbit/s connection to a PC
- TDLink: Optical link (4.25 Gbit/s) with synch distribution. Allows for multi-board synchronization, slow control and data readout (COMING SOON)
- POWER REQUIREMENTS
Single power supply (+12 V). Regularly working in a range between +7 V and +15 V
- POWER CONSUMPTIONS
750 mA @ +12 V, i.e. ≈ 9 W (acquisition on, all channels enabled, HV on, 64 SiPMs mounted)
685 mA @ +12 V, i.e. ≈ 8.2 W (acquisition off, all channels enabled, HV off, no SiPMs mounted)
- FIRMWARE
Firmware can be upgraded via USB or Ethernet
- SOFTWARE
Fully controlled by the Janus software on Windows®

- Documentation
- Software
- Firmware
Free
Data Sheet
Manuals
Driver
Application SW
Scientific Articles
Application Notes
Slide Presentations
Compare
Compare with:
Loading...
Ordering Options
Code | Description |
---|---|
WDT5202XAAAA | DT5202 - Desktop 64 Channel Citiroc unit for FERS-5200 RoHS |