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A5204

Coming Soon

64 Channel Radioroc unit for FERS-5200

Features

  • 64-ch frontend unit for SiPM readout and high resolution timing applications housing a Weeroc Radioroc ASIC and a CERN picoTDC chip
  • Part of FERS-5200, the CAEN platform for the readout of large arrays of detectors (SiPM, MA-PMTs, Gas Tubes, Si detectors, …)
  • Onboard A7585D SiPM power supply for sensors biasing
  • Acquisition modes: Spectroscopy (PHA), Counting, Timing with ToT
  • Scalability and easy-synch: up to 128 cards (8192 channels) can be managed and synchronized by a single DT5215 Concentrator Board, thanks to the optical TDlink
  • Janus 5204 open source software available for board configuration and DAQ control
  • Flexibility: a full range of adapters and cables for different kind of SiPMs and sensors remotization
  • Boxed FERS unit (DT5204) for desktop use or naked (A5204) for customizable mechanical frame

Overview

FERS-5200 is a front‐end readout system designed for the readout of large detector arrays, such as SiPMs, multi‐anode PMTs, Silicon Strip detectors, Wire Chambers, GEMs, Gas Tubes and others. FERS‐5200 is a distributed and scalable system, where each unit is a small card that houses 64 or 128 channels. It features a detector specific Front-End interfaced to a common infrastructure that guarantees readout interfaces, slow control and synchronization. Typically, the front-end is based on ASIC chips that allow for high density, cost effective integration of multi-channel readout electronics into small size and low power modules. FERS is a flexible platform: combining the same back-end (i.e. readout architecture and interface) with different types of front-end to fit a wide range of detectors.

The A5204 (and DT5204, which is the boxed version for desktop use) is a member of the FERS-5200 family. It uses the Radioroc chip (produced by Weeroc) for the readout of SiPM detectors. Radioroc allows triggering down to 1/3 p.e. and provides dual-gain energy measurement with excellent Signal-to-Noise Ratio on the high gain (SNR over 10 for single p.e.) and large dynamic range on the low gain. Thanks to the programmable shaping time, that can be different for low and high gain, the Radioroc can perform Pulse Shape Discrimination with organic and inorganic scintillators coupled to SiPMs.

The A5204 includes a High Voltage generator (up to +80V, 10 mA) for the SiPM biasing; a channel-by-channel 8-bit DAC contained in the Radioroc ASIC allows for fine adjustment of the SiPM bias voltage and SiPM gains homogenization. Besides the slow shaper + peak sensing chain for the acquisition in spectroscopy mode, Radioroc includes configurable fast pre-amplifiers followed by discriminators that can output 64 individual channel triggers with jitter as low as 55 ps FWHM on a single p.e. The individual channel triggers are connected to the FPGA, for photo-counting up to 200 MHz as well as for the implementation of coincidences, majority and topological acquisition triggers. The individual triggers are also connected to a picoTDC, an ASIC chip produced by CERN, implementing a 64 channel TDC with LSB = 3.125 ps, for very precise timing measurements. Time Over Threshold (ToT) can also be used to estimate the pulse height, making it possible to acquire time stamp and PHA with very low dead time and extremely high rate, without the need of the multiplexed A/D conversion.

For small setups a single A5204 unit can be used stand alone, without any additional hardware, by simply connecting the unit to a PC via USB 2.0 or Ethernet 10/100BASE-T. For large readout systems, a flexible and scalable network of units can be created by means of the high speed optical link called TDlink. The TDlink system supports up to 128 FERS units to be connected to and managed by one DT5215 FERS Data Concentrator Module. The TDlink supports optical daisy chaining and provides slow control, high speed data readout, synchronization between the units (clock and sync distribution), as well as command broadcasting for triggers, time resets, etc.

The A5204 is fully supported by the CAEN Janus 5204 Open Source software on Windows® and Linux®. Janus can run in console mode (C program, without graphics) or connected to a GUI written in Python. The GUI has configuration and run control panels that simplify the data acquisition management. Both console and GUI modes acquire data from multiple boards, manage configuration, event building, PHA and timing histograms (deltaT and/or ToT), display data statistics (hit rate, throughput, etc…), plot histograms, and save output, including spectra and list files with the acquired timing data.

A wide range of adapters and cables has been also specifically designed for FERS-5200 boards, in order to provide versatility of choice and the ability to remotely operate the detectors, a complete list is available here.

Technical Specifications

MECHANICAL
Weight Dimension
161 g (A5204 with spacers mounted); 72.8 W x 22.0 H x 208.5 L mm3
INPUTS
64 channels
Input edge connector type Samtec HSEC8-170
Mating connector: Samtec HSEC8-170-01-S-DV
Signal polarity: Positive
Each SiPM input has two pins:
  • Cathode with HV bias (min = +20V, max = +80V)
  • Anode closed to ~100 ohm, feeding the Radioroc inputs
HIGH VOLTAGE (SiPM Bias)

HV module for SiPM biasing (A7585D)
HV Range: +20V/+80V, Max 10 mA
Individual bias adjustment on channel basis (8 bit DACs, LSB = ~2 mV, adjust range = 550 mV)
Automatic temperature feedback for SiPM gain stabilization

ACQUISITION MODES

Spectroscopy:

The common trigger initiates the peak sensing detection and A/D conversion (12 bit) on all channels simultaneously. Conversion time = ~10 μs. Output Data: Trigger time stamp, Trigger ID, PHA (Low and/or High Gain). Zero suppression with programmable threshold.

Counting:

32 bit counters, up to 200 MHz. Common trigger defines dwell time (i.e. counting window). No dead-time between subsequent windows. Internal period trigger from 16 ns to ~34 s. Output Data: Trigger time stamp, Trigger ID, channel counts. Zero suppression available. Counters are automatically reset after each trigger.

Timing (Common Start):

The Tref signal (T0, T1 inputs) is a common start that opens the acquisition gate with programmable width. Channel self-triggers are acquired as T from Tref and, optionally, as ToT for PHA estimation. Output Data: Trigger (=Tref) time stamp, Trigger ID, T or T+ToT

Timing (Common Stop):

Same as common start, with Tref used as a common stop that closes the acquisition gate. Acquired events are those ones arrived before the trigger (look back acquisition).

Timing (Trigger Matching):

The common trigger signal defines an acquisition window with programmable width and offset. All hits falling into the window will be recorded. Multi-hit acquisition is supported. Output Data: Trigger time stamp, Trigger ID, ToA or ToA+ToT

Timing (Streaming):

Continuous hit recording, without any gate or trigger windowing. All hit time measurements are expressed as 64 bit time stamps and saved in the form of a sorted list. Output Data: ToA or ToA+ToT

SENSITIVITY (GAIN) - SPECTROSCOPY

High Gain: Min = 5, Max = 80, 16 steps (1 step = 5)

Low Gain: Min = 0.5, Max = 8, 16 steps (1 step = 0.5)

SHAPING TIME - SPECTROSCOPY

Short Range: Min = 20 ns, Max = 300 ns, 16 steps (1 step = 20 ns)

Long Range: Min = 80 ns, Max = 1200 ns, 16 steps (1 step = 80 ns)

DYNAMIC RANGE - SPECTROSCOPY

Up to 2000 photo-electrons @ 106 SiPM gain

SELF TRIGGERS - TIMING & COUNTING

Dedicated fast preamps + discriminator for SiPM pulse detection. Trigger down to 1/3 p.e.

Fast Preamp Gain: Min = 15 (BW = 480 MHz), Max = 100 (BW = 55 MHz), 32 steps Discriminator Dual Threshold: Range = 278 mV; 1024 steps, 1 step = 0.27 mV

TIMING RESOLUTION - TIMING & COUNTING

55 ps FWHM on a single p.e.

Time Stamp Range: 64 bit

Intrinsic timing resolution of picoTDC = 3.125 ps LSB

ToT - TIMING & COUNTING

Time over Threshold (ToT): 1% linearity energy measurement up to 2000 p.e.

COUNTING - TIMING & COUNTING

Photon counting up to 200 Mcps per channel

MCS mode with programmable dwell time: from 16 ns to ~34 s

TRIGGER LOGIC

Global trigger common to 64 channels: used in Spectroscopy mode to start Peak acquisition, in Timing mode to generate the acquisition windows (Gate). Trigger-less acquisition only in Streaming mode.

Global Trigger Sources:

  • OR of self-triggers = OR(0..63)
  • Plane coincidence: OR(0..31) AND OR(32..63)
  • Paired channels: AND(0..1) OR AND(2..3) … OR AND(62..63)
  • Majority with programmable threshold
  • External trigger (T0-IN, T1-IN, LEMO, TTL/NIM)
  • Internal periodic trigger with programmable frequency
TIME STAMP & SYNCHRONIZATION

Acquisition Trigger Time Stamp: 56 bit, step = 8 ns

Two synchronization modes:

  • T0 or T1 IN-OUT daisy chain: max jitter = 100 ns
  • fiber optic (TDlink) and DT5215 Concentrator: up to 128 boards, max jitter 50 ps
FRONT PANEL I/Os

T0-IN, T1-IN: LEMO-00 connector, NIM or TTL (terminated to 50 Ω)

T0-OUT, T1-OUT: LEMO-00 connector, TTL (50 Ω termination required)

SW selectable IN-OUT bypass and termination removal for daisy chaining

Functions (SW programmable):

Trigger, Acquisition Start/Stop, Sync, Busy, Veto, Signal inspection, etc…

FRONT PANEL LEDs

GREEN: Power-ON, Init-Done, Run, Trigger, Data Ready, T0-IN, T1-IN

ORANGE: Event Overrun (rejected triggers because received while busy)

RED: Failure (missing clock, over-temperature, etc…)

INTERNAL PULSER

Radioroc provides a test input pin that can be internally connected to the pre-amplifier inputs, channel by channel. The test signal can come from an external signal (MCX connector on the PCB) or generated by an internal pulser with programmable amplitude. The internal pulser can be trigger by T0/T1 IN or by the internal periodic trigger.

COMMUNICATION INTERFACES
USB Ethernet Optical Link
USB2.0: microUSB connector

Bandwidth = ∼ 3 MB/s

Ethernet connector, type Rj-45. Supports 10/100 Mbit/s connection to a PC

Bandwidth = ∼ 2.5 MB/s

Small Form Factor Pluggable (SFP+) transceiver component for optical connection (3.125 Gbit/s).

TDlink CAEN proprietary protocol allows for multi-board synchronization, slow control and data readout

Data Concentrator DT5215 required

FIRMWARE

Firmware of FPGA be upgraded via USB or Ethernet
Firmware of μC can be upgraded via Ethernet only

SOFTWARE

Readout SW
Fully controlled by the Janus 5204 open source software for Windows® and Linux®.
It can run in console mode (C program, with console commands and gnuplot display for plots) or connected to a GUI (Python) that implements user friendly configuration panels and run controls.

Janus 5204 can perform multiple board acquisition of  PHA energy spectrum (Low and High Gain). ToT spectrum (represents PHA in timing mode) DT spectrum, with event building based on trigger ID or time stamp.

Live Display: channel hit count and rate, trigger rate, lost triggers, data throughput, acq. time, etc… Plots: PHA, DT, ToT, hit rate, 2-D heat map with channel hit rates or PHA.

Output Files: histograms (spectra), list files (PHA, ToA, ToT, DT), Run Info, Sync file.

 

Web Interface
Board information and monitoring, Ethernet configuration.

POWER REQUIREMENTS
Single power supply (+12 V). Regularly working in a range between +7 V and +15 V
110V/220V AC/DC converter provided with Desktop version only.
POWER CONSUMPTIONS

t.b.d.

Compare

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Accessories

A5251
Hamamatsu MPPC header adapter for A5202/DT5202
A5253
3-pin header adapter for A5202/DT5202
A5260
Remotization cable for FERS-5200 boards
A5261
SiPM remotization cable (0.7 m) for A5253
A5254
OnSemi (ex SensL) ARRAY J/C header adapter for A5202/DT5202
A5270
FERS cooling fan

Ordering Options

Code Description
WA5204XAAAAA A5204 – 64 channel Radioroc unit for FERS-5200 with picoTDC  RoHS
WA5204BXAAAA A5204B- 64 channel Radioroc unit for FERS-5200   RoHS

Contacts

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