128 Channel Multihit TDC (100/200/800 ps)
- 3 programmable ranges: 100 ps LSB (19 bit resolution), 200 ps LSB (19 bit) and 800 ps LSB (17 bit)
- ECL/LVDS inputs automatically detected
- 5 ns Double Hit Resolution
- Leading and Trailing Edge detection
- Trigger Matching and Continuous Storage acquisition modes
- 32 k x 32 bit output buffer
- MBLT, CBLT and 2eSST data transfer
- Multicast commands
- Live insertion
- Libraries, Demos (C and LabView) and Software tools for Windows and Linux
The V1190A-2eSST is a 128 channel Multihit TDC, housed in a 1-unit wide VME 6U module. The unit features High Performance Time to Digital Converter chips developed by CERN. LSB can be set at 100 ps (19 bit resolution, 52 µs FSR), 200 ps (19 bit, 104 µs FSR) or 800 ps (17 bit, 104 µs FSR).
The channels can be enabled for the detection of hits rising/falling edges or for their width measurement (both the edges’ timing, and the hit width can be measured with the selected resolution). For each channel there is a digital adjustment for the zero-ing of any offsets. The data acquisition can be programmed in “Events” (“Trigger Matching Mode”, with a programmable time window) or in “Continuous Storage Mode”. Both ECL and LVDS input signals are supported.
The module programming is performed via a microcontroller that implements a high-level user friendly interface. The VME interface allows the module to work in A24 and A32 addressing modes.
The board houses a 32 k x 32 bit deep Output Buffer that can be readout via VME in a completely independent way from the acquisition itself.
The device supports MBLT, CBLT and 2eSST readout modes. Live insertion is also supported.
6U-high, 1U-wide VME unit
128 ECL/LVDS inputs, 110 Ohm impedance
- Double hit resolution
- Acquisition modes
Trigger Matching Mode; Continuous Storage Mode
- Built-in memory
32 kwords deep Output Buffer
- Trigger Window Width
Programmable from 25 ns to 100 µs
800, 200, 100 ps (selectable)
- Dynamic Range
104 µs (200 ps and 800 ps LSB); 52 µs (100 ps LSB)
- RMS resolution
<320 ps @ 800 ps res.
<140 ps @ 200 ps res.
<80 ps @ 100 ps res.
- Integral non linearity
<0.3 LSB @ 800 ps res.
<1 LSB @ 200 ps res.
<1 LSB @ 100 ps res.
- Differential non linearity
<0.2 LSB @ 800 ps res.
<0.3 LSB @ 200 ps res.
<0.5 LSB @ 100 ps res.
- Interchannel Isolation
- Offset spread
- EXT TRIGGER input
Two LEMO 00 bridged connectors, ECL signal, 110 Ohm
- Clock source
Internal (40 MHz) or External (on Control connector), dip switch selectable
- Control inputs
active-high, differential ECL input signals:
RST: resets Output Buffer, Status and Control registers.
CLR: FAST CLEAR of TAC sections rising-edge active,
differential ECL input signals:
CLK: external clock
TRG: trigger for the TDC latching
- Control outputs
differential ECL output signal:
OUT_PROG: control output signal, programmable via the out prog control register
DTACK: green LED; lights up at each VME access.
PWR: green/red LED; green: power ON, red: failure status.
TERM: green LED; control bus termination ON.
FULL: red LED; memory full. ERROR: red LED; TDC global error.
DRDY: yellow LED; at least one datum in the output buffer
Addressing modes: A24, A32, MCST Data transfer modes: D16, D32, BLT32, BLT64, CBLT, 2eSST
128 Channel Multihit TDC (100/200/800 ps)Product page
|Name||File extension||File size||Revision||Date|
|V1190_REV_1.1.RBF||RBF||163.05 kB||1.1||February 10th, 2016|
|Name||File extension||File size||Revision||Last update|
|V1190A/B-VX1190A/B - 128/64 Channel Multihit TDCs||2.26 MB||14||November 29th, 2016|
|High Performance Time to Digital Converter v2.2 User Manual (for HPTDC version 1.3)||1.23 MB||2||March 1st, 2004|
|Precautions for Handling Storage Installation (ENG/ITA)||179.29 kB||-||April 10th, 2019|
Compare with TDCs.
|WV1190AEXAAE||V1190A - 2ESST 128 Ch. Multievent Multihit TDC 100-200-800 psec ECL/LVDS (no JAUX)|