V1190A-2eSST

6U-high, 1U-wide VME unit

128 ECL/LVDS inputs, 110 Ω impedance

5 ns

Trigger Matching Mode; Continuous Storage Mode

32 kwords deep Output Buffer

Programmable from 25 ns to 100 µs

800, 200, 100 ps (selectable)

104 µs (200 ps and 800 ps LSB); 52 µs (100 ps LSB)

• <320 ps @ 800 ps res.
• <140 ps @ 200 ps res.
• <80 ps @ 100 ps res.

• <0.3 LSB @ 800 ps res.
• <1 LSB @ 200 ps res.
• <1 LSB @ 100 ps res.

• <0.2 LSB @ 800 ps res.
• <0.3 LSB @ 200 ps res.
• <0.5 LSB @ 100 ps res.

≤0.7 LSB

<2 ns

Two LEMO 00 bridged connectors, ECL signal, 110 Ohm

Internal (40 MHz) or External (on Control connector), dip switch selectable

Active-high, differential ECL input signals:

• RST: resets Output Buffer, Status and Control registers.
• CLR: FAST CLEAR of TAC sections rising-edge active,
  differential ECL input signals:
• CLK: external clock
• TRG: trigger for the TDC latching

differential ECL output signal:
OUT_PROG: control output signal, programmable via the out prog control register

• DTACK: green LED; lights up at each VME access.
• PWR: green/red LED; green: power ON, red: failure status.
• TERM: green LED; control bus termination ON.
• FULL: red LED; memory full. ERROR: red LED; TDC global error.
• ERROR: red LED; TDC global error.
• DRDY: yellow LED; at least one datum in the output buffer

Addressing modes: A24, A32, MCST Data transfer modes: D16, D32, BLT32, BLT64, CBLT, 2eSST