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DT5740D

32 Channel 12 bit 62.5MS/s Digitizer supporting DPP-QDC firmware

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Features

  • 12 bit 62.5 MS/s ADC
  • 32 / 16 channels
  • ERNI SMC Dual Row 68pin connector (32 channels)
  • Auxiliary ERNI SMC Dual Row 68pin connector
  • MCX connectors (16 channels by using auxiliary SMC)
  • 2 Vpp single ended input range
  • 16-bit programmable DC offset adjustment: ±1 V
  • Trigger Time stamps
  • Memory buffer: 192 kS/ch, up to 1024 events
  • FPGA for real-time data processing:
  • Programmable event size and pre-post trigger adjustment
  • Optical Link interface (CAEN proprietary protocol)
  • USB 2.0 compliant interface
  • Firmware upgradeable via USB or Optical Link
  • Caen DPP-QDC demo software (windows only) with C source file for developers
  • External AC-DC Power Supply Adapter (+12 V)
  • Dimensions: 154x50x164 mm3 (WxHxD)
More info
3 Years Warranty
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Overview

The CAEN Mod.DT5740D is a 32 Channel 12 bit 62.5 MS/s (65 MS/s using external clock) Desktop Waveform Digitizer with 2 Vpp single ended input dynamics on ERNI SMC connectors. 16 channels are available also on MCX coaxial connectors. The DC offset is adjustable via a 16-bit DAC on each 8-channel group in the ±1 V range.
The module features front panel Clock Input and a PLL for clock synthesis from internal/external references. The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read by USB or Optical Link. The acquisition can continue without dead time in a new buffer.
Each channel has a SRAM Multi-Event Buffer of 192 kS divisible into 1 ÷ 1024 buffers of programmable size. The readout (by USB or Optical Link) of a frozen buffer is independent from the write operations in the active circular buffer (ADC data storage).
DT5740D supports multi-board synchronization allowing all ADCs to be synchronized to a common clock source and ensuring Trigger time stamps alignment. Once synchronized, all data will be aligned and coherent across multiple DT5740D boards.
The trigger signal can be provided externally via the front panel Trigger Input as well as via the software, but it can also be generated internally thanks to threshold self-trigger capability.
DT5740D houses USB 2.0 and Optical Link interfaces. USB 2.0 allows data transfers up to 30 MB/s. The Optical Link supports transfer rate of 80 MB/s and offers Daisy chain capability. Therefore, it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod. A2818/A3818).

Software available (Windows and Linux):
CAEN provides drivers for all the different types of physical communication channels, a set of C and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:

  • CAENUpgrader: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.

Standard Firmware compliant:

  • CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.

Digital Pulse Processing firmware for Physics Applications – this special firmware allows to perform on-line processing on detector signal directly digitizer:

Technical Specifications

GENERAL

Weight: 680 gr
Desktop module: 154x50x164 mm3 (WxHxD)

ANALOG INPUT
  • 32 channels (ERNI SMC Dual Row 68pin connector) or 16 channels (MCX coaxial connectors, 50 Ω)
  • Single-ended
  • Bandwidth: 30 MHz
  • Input range: 2 Vpp
  • Programmable DAC for Offset Adjustment (one for each 8-channel group): ±1 V
  • Absolute max. input voltage: 6 Vpp with Vrail max. to +6V or -6V for any DAC offset value
DIGITAL CONVERSION

Resolution: 12 bit
Sampling rate: up to 62.5 MS/s simultaneously on each channel (65 MS/s using external clock)

SYSTEM PERFORMANCE
  • ENOB: 11.20 (48 kS Buffer)
  • SINAD: 69.20 dB
  • THD: 87.10 dB
  • SFDR: 94.9 dB
  • SIGMA: 0.50 LSB rms (48 kS Buffer, open input)
ADC Sampling Clock generation

Three operating modes:

  • PLL mode: internal reference (62.5 MHz loc. oscillator)
  • PLL mode: external reference on CLK_IN
  • PLL Bypass mode: ext. clock on CLK_IN drives directly ADC clocks (Freq.: 10 ÷ 65 MHz)
DIGITAL I/O
  • CLK_IN (AMP Modu II):
    – AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by custom cable)
    – Jitter < 100ppm
  • TRG_IN (LEMO 50 Ohm, NIM/TTL): external trigger input
  • GPI/GPO (LEMO 50 Ohm, NIM/TTL): programmable front panel input/output
MEMORY BUFFER
  • 192 kS/ch Multi Event Buffer
  • Programmable event size and pre-post trigger
  • Divisible into 1 ÷ 1024 buffers
  • Readout of Frozen buffer independent from write operations in the active buffer (ADC data storage)
TRIGGER

Common Trigger:

  • External (signal on TRG_IN)
  • Software (by USB or Optical Link)
  • Self trigger (internal threshold self-trigger generated by each 8-channel group)

Daisy chain trigger propagation among boards (using GPO)

TRIGGER Time Stamp

31-bit counter, 16 ns resolution, 17 s range(*)
(*)Trigger Logic and Trigger Time Stamp counter operate at 125 MHz (i.e. 8 ns or 1/2 ADC clock cycles), while the counter value is read at a frequency of 62.5 MHz (i.e. 16 ns).

MULTI MODULES SYNCHRONIZATION
  • Clock distribution: by Fan Out
  • Trigger distribution: by Daisy chain or Fan Out
  • Time stamp synchronization
ADC AND MEMORY CONTROLLER FPGA

One Altera Cyclone EP3C40 per 16 channel

USB INTERFACE
  • USB2.0 compliant
  • Up to 30 MB/s transfer rate
OPTICAL LINK

CAEN CONET proprietary protocol Up to 80 MB/s transfer rate
Daisy‐chain: it is possible to connect up to 8 or 32 ADC modules to a single Optical Link Controller (respectively A2818/A4818 or A3818/A5818)

UPGRADE
  • Firmware can be upgraded via Optical Link or USB interface
SOFTWARE
  • Caen DPP-QDC demo software (windows only) with C source file for developers
ELECTRICAL POWER
  • Voltage range: 12 ± 10% Vdc. Power consumption (typ.): 1.9A @12V

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A317
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Ordering Options

Code Description
WDT5740DXAAA DT5740D - 32 Ch. 12 bit 62.5 MS/s Digitizer: 192kSch, EP3C40, SE   RoHS

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