16 Channel Dual Range Multievent QDC
- Two simultaneous ranges: 0 ÷ 900 pC and 0÷100 pC
- 12 bit resolution with 15 bit dynamics
- 25 fC LSB on low range, 200 fC LSB on high range
- 5.7 µs / 16 ch conversion time
- 600 ns fast clear time
- Zero and overflow suppression for each channel
- ±0.1 % Integral non linearity
- ±1.5 % Differential non linearity
- 32 event buffer memory
- BLT32/MBLT64/CBLT32/CBLT64 data transfer
- Multicast commands
- Live insertion
- Libraries, Demos (C and LabView) and Software tools for Windows and Linux
The Mod. V965 is a 1-unit wide VME 6U module housing 16 Charge-to-Digital Conversion channels with current integrating negative inputs (50 Ohm impedance). For each channel, the input charge is converted to a voltage level by a QAC (Charge to Amplitude Conversion) section. Each QAC output is then converted by two ADCs in parallel; one ADC is preceded by a x1 gain stage, the other by a x8 gain stage: a dual input range is then featured: 0 ÷ 900 pC (200 fC LSB) and 0 ÷ 100 pC (25 fC LSB); this allows to avoid saturation with big charge pulses while increasing resolution with small ones.
The outputs of the QAC sections are multiplexed and subsequently converted by two fast 12-bit ADCs. The ADCs use a sliding scale technique to improve the differential non-linearity. Programmable zero suppression, multi-event buffer memory, trigger counter and test features complete the flexibility of the unit.
The module works in A24/A32 addressing mode; the data transfer occurs in D16/D32/BLT32/MBLT64. The module also supports the chained block transfer (CBLT32/CBLT64) and the multicast commands.
The board supports the live insertion that allows inserting or removing it into the crate without switching it off.
1-unit wide 6U VME module
16 channels, 50 Ohm impedance, negative polarity, DC coupling
- Input range
Dual range: 0 ÷ 900 pC / 0÷100 pC
12 bit (15 bit dynamics)
High range: 200 fC/count; Low range: 25 fC/count
- Max. tolerated positive voltage input
< 5% with 2 ns fall time input signals
- Input offset
- RMS Noise
0.5 counts typical
- Integral non linearity
0.1% of FSR (=3840 counts)
from 5% to 95% of FSR
- Interchannel gain uniformity
- Interchannel gain uniformity
> 60 dB
- Power rejection
0.002 count/mV (+5V); 0.01 count/mV (-5V)
0.0046 count/mV (+12V); 0.0012 count/mV (-12V)
- Fast clear time
- Gate timing
the Gate signal must precede the analog input by > 15 ns
- Conversion time
5.7 µs for all channels
- Zero suppression
Treshold values programmable in:
16 ADC counts steps over the entire FSR
2 ADC counts steps over 1/8 of FSR
- Control inputs
NIM input signals:
GATE: temporal window for current integration .
RST: resets QAC sections, MEB status and control registers.
VETO: inhibits the conversion of the QAC signals.
FCLR: FAST CLEAR of QAC sections.
- Control outputs
NIM output signals:
DRDY: indicates the presence of data
BUSY: board full, resetting, converting or in MEMORY TEST mode
- VME interface
16 Channel Dual Range Multievent QDCProduct page
|Name||File extension||File size||Revision||Last update|
|V965/V965A - 16/8 Channel Dual Range Multievent QDC||390.01 kB||8||November 2nd, 2015|
|Precautions for Handling Storage Installation (ENG/ITA)||179.29 kB||-||April 10th, 2019|
|Name||File extension||File size||Revision||Last update||OS||OS Version|
|CAENQTPD Data Acquisition (DAQ) demo software||ZIP||26.57 MB||1.0||May 5th, 2019||Windows||
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