16 Channel Multievent QDC
- High channel density
- 12bit resolution
- 2.8 µs / 16 ch conversion time
- 600 ns fast clear time
- Zero and overflow suppression for each channel
- ±1.5% differential non linearity
- ±0.1% integral non linearity
- 32 event buffer memory
- BLT32/MBLT64/CBLT32/CBLT64 data transfer
- Multicast commands
- Live insertion
- Libraries, Demos (C and LabView) and Software tools for Windows and Linux
The Model V792N is a 1-unit wide VME 6U module housing 16 Charge-to-Digital Conversion channels with current integrating negative inputs (50 Ohm impedance).
For each channel, the input charge is converted to a voltage level by a QAC (Charge to Amplitude Conversion) section. Input range is 0 ÷ 400 pC.
The Model V792N features LEMO 00 connectors for both input and control signals. The outputs of the QAC sections are multiplexed and subsequently converted by two fast 12-bit ADCs. The integral non linearity is ±0.1% of Full Scale Range (FSR) measured from 5% to 95% of FSR. The ADCs use a sliding scale technique to improve the differential non-linearity.
The Mod. V792N offers a 32 event buffer memory, A24/A32 addressing mode, D16, D32, BLT32/MBLT64 and CBLT32/CBLT64 data transfer mode. Multicast commands are also supported.
The board supports the live insertion that allows inserting or removing them into the crate without switching it off.
1-unit wide 6U VME module (version NA requires the V430 backplane)
16 channels, 50 Ohm impedance, negative polarity, DC coupling
- Input range
0 ÷ 400 pC (if Sliding Scale is used FSR is reduced from 4095 to 3840 counts)
- Max. tolerated positive voltage input
< 5% with 2 ns fall time input signals
- Input offset
- RMS Noise
0.5 counts typical
- Integral non linearity
0.1% of FSR (=3840 counts)
from 5% to 95% of FSR
- Interchannel gain uniformity
- Interchannel gain uniformity
> 60 dB
- Power rejection
0.002 count/mV (+5V); 0.01 count/mV (-5V)
0.0046 count/mV (+12V); 0.0012 count/mV (-12V)
- Fast clear time
- Gate timing
the Gate signal must precede the analog input by > 15 ns
- Conversion time
2.8 µs for all channels
- Zero suppression
Treshold values programmable in:
16 ADC counts steps over the entire FSR
2 ADC counts steps over 1/8 of FSR
- Control inputs
NIM input signals:
GATE: temporal window for current integration .
RST: resets QAC sections, MEB status and control registers.
VETO: inhibits the conversion of the QAC signals.
FCLR: FAST CLEAR of QAC sections.
- Control outputs
NIM output signals:
DRDY: indicates the presence of data
BUSY: board full, resetting, converting or in MEMORY TEST mode
- VME interface
16 Channel Multievent QDCProduct page
|Name||File extension||File size||Revision||Last update|
|V792/V792N - 32/16 Channel Multievent QDC||566.86 kB||18||November 4th, 2010|
|Precautions for Handling Storage Installation (ENG/ITA)||179.29 kB||-||April 10th, 2019|
|Name||File extension||File size||Revision||Last update||OS||OS Version|
|CAENQTPD Data Acquisition (DAQ) demo software||ZIP||26.57 MB||1.0||May 5th, 2019||Windows||
Compare with QDCs.
|WV792XNCAAAA||V792NC - 16 Channel Multievent Charge ADC (No JAUX, No 12V DCDC, live ins) RoHS|