8 Ch Dual Range Multievent Peak Sensing ADC
- Two simultaneous ranges: 0 ÷ 4 V / 0 ÷ 500 mV
- 12 bit resolution with 15 bit dynamics
- 125 µV LSB on low range, 1mV LSB on high range
- 2.8 µs / 8 ch conversion time
- 600 ns fast clear time
- Zero and overflow suppression for each channel
- ±0.1 % Integral non linearity
- ±1.5 % Differential non linearity
- 32 event buffer memory
- BLT32/MBLT64/CBLT32/CBLT64 data transfer
- Multicast commands
- Live insertion
The Mod. V1785 is a 1-unit wide VME 6U module housing 8 Peak Sensing Analog-to-Digital Conversion channels. Each channel is able to detect and convert the peak value of the positive analog signals (with >50 ns risetime) fed to the relevant connectors. Input voltage range is 0 ÷ 4 V. Each channel is processed by two gain stage (x1 and x8) in parallel followed by the ADC stage: a dual input range is then featured: 0 ÷ 4 V (1 mV LSB) and 0 ÷ 500 mV (125 μV LSB); this allows to avoid saturation with big input signals while increasing resolution with small ones.
The ADCs use a sliding scale technique in order to reduce the differential non-linearity.
Programmable zero suppression, multievent buffer memory, trigger counter and test features complete the flexibility of the unit.
The module works in A24/A32 mode. The data transfer occurs in D16, D32, BLT32 or MBLT64 mode. The unit supports also the Chained Block Transfer (CBLT32/CBLT64) and the Multicast commands.
The VME interface is VME64 and VME64X standard compliant and features the A24/A32 and MultiCast addressing modes. The data readout occurs either in D32, BLT32, MBLT64 mode, or in daisy chain with 32/64 bit Chained Block Transfers. The module features a fully programmable RORA interrupter.
The board is provided with the P1 and P2 VME connectors and fits into both V430 and standard 6U crates. It also supports the “live insertion”,
allowing the User to insert (or remove) the board into (or from) the crate without switching it off.
1-unit wide 6U VME module
8 channels, 1 kohm impedance, positive polarity, DC coupling
- Input range
Dual range: 0 ÷ 4 V / 0 ÷ 500 mV
12 bit (15 bit dynamics)
High range: 1 mV/count; Low range: 125 µV/count
- Min. input voltage
< 5% with 2 ns fall time input signals
- Input offset
- RMS Noise
0.7 counts (high range), 1.5 counts (low range)
- Integral non linearity
± 0.1% of FSR (=3840 counts)
from 5% to 95% of FSR
- Interchannel gain uniformity
- Interchannel gain uniformity
> 60 dB
- Fast clear time
- Conversion time
2.8 µs for all channels
- Zero suppression
Treshold values programmable in:
16 ADC counts steps over the entire FSR
2 ADC counts steps over 1/8 of FSR
- Control inputs
NIM input signals:
GATE: temporal window for current integration .
RST: resets QAC sections, MEB status and control registers.
VETO: inhibits the conversion of the QAC signals.
FCLR: FAST CLEAR of QAC sections.
- Control outputs
NIM output signals:
DRDY: indicates the presence of data
BUSY: board full, resetting, converting or in MEMORY TEST mode
- VME interface
8 Ch Dual Range Multievent Peak Sensing ADCProduct page
|Name||File extension||File size||Revision||Last update|
|V1785 8 Ch Dual Range Multievent Peak Sensing ADC||315.60 kB||5||September 3rd, 2015|
|Precautions for Handling Storage Installation (ENG/ITA)||179.29 kB||-||April 10th, 2019|
|Name||File extension||File size||Revision||Last update||OS||OS Version|
|CAENQTPD Data Acquisition (DAQ) demo software||ZIP||26.57 MB||1.0||May 5th, 2019||Windows||
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