32 Channel Multihit TDC (25 ps)
- 25 ps LSB
- 21 bit resolution
- 52 µs full scale range
- ECL/LVDS Input Signals
- 5 ns Double Hit Resolution
- Trigger Matching and Continuous Storage acquisition modes
- Leading and/or Trailing Edge detection
- 32 k x 32 bit output buffer
- MBLT, CBLT and 2eSST data transfer
- Multicast commands
- Live Insertion
The CAEN Mod. V1290A-2eSST is a 32 channel Multihit TDC, housed in a 1-unit wide VME 6U module. The unit features High Performance Time to Digital Converter chips developed by CERN. LSB is 25 ps (21 bit resolution, 52 µs FSR). The module accepts both ECL and LVDS inputs.
The channels can be enabled for the detection of hits rising/falling edges. For each channel there is a digital adjustment for the zero-ing of any offsets. The data acquisition can be programmed in “Events” (“Trigger Matching Mode”, with a programmable time window) or in “Continuous Storage Mode”.
The module programming is performed via a microcontroller that implements a high-level user friendly interface. The VME interface allows the module to work in A24 and A32 addressing modes.
Conn Header R/A 64pos 2.54mm for Mod. V1290A-2eSST
Consult our connectors reference page for technical information.
The board houses a 32 k x 32 bit deep Output Buffer, that can be readout via VME in a completely independent way from the acquisition itself.
The device supports MBLT, CBLT and 2eSST readout modes. Live insertion is also supported.
6U-high, 1-unit wide, VMEx64X unit
32 ECL / LVDS inputs, 110 Ohm impedance
- Double hit resolution
- Acquisition modes
Trigger Matching Mode; Continuous Storage Mode
- Built-in memory
32 kwords deep Output Buffer
- Dynamic Range
- RMS resolution (with compensation enabled)
35 ps (typical)
- Integral non linearity (with compensation enabled)
- Max. differential non linearity (with compensation5 disabled)
- Interchannel Isolation
- Offset spread
- EXT TRIGGER input
Two LEMO 00 bridged connectors, NIM signal, 50 Ohm
- Double Trigger resolution
- Clock source
Internal (40 MHz) or External (on Control connector), dip switch selectable
- Control inputs
active-high, differential ECL input signals:
CLR: performs the Hardware CLEAR (min. width: 25 ns)
rising-edge active, differential ECL input signals:
CRST: performs the Bunch RESET (min. width: 25 ns)
CLK: external clock (max. freq.: 40 MHz)
TRG: trigger for the TDC latching (min. width: 25 ns)
- Control outputs
differential ECL output signal:
OUT_PROG: control output signal, programmable via the
out prog control register
DTACK: green LED; lights up at each VME access.
PWR: green/red LED; green: power ON, red: failure status.
TERM: green LED; control bus termination ON.
FULL: red LED; memory full.
ERROR: red LED; TDC global error.
DRDY: yellow LED; at least one datum/event in the Output Buffer
Addressing modes: A24, A32, MCST
Data modes: D16, D32, MBLT32, BLT64, CBLT32, CBLT64, 2eVME, 2eSST7
Readout rate: up to 120 Mbyte/s with 2eSST
32 Channel Multihit TDC (25 ps)Product page
|Name||File extension||File size||Revision||Date|
|V1190_REV_1.1.RBF||RBF||163.05 kB||1.1||February 10th, 2016|
|Name||File extension||File size||Revision||Last update|
|V1290/VX1290||2.37 MB||16||November 29th, 2016|
|High Performance Time to Digital Converter v2.2 User Manual (for HPTDC version 1.3)||1.23 MB||2||March 1st, 2004|
|Safety Information and Product Support Service (ENG/ITA)||1.83 MB||-||July 24th, 2023|
Compare with TDCs.
|WV1290AEXAAE||V1290A - 2ESST 32 Ch. Multievent Multihit TDC 25 psec ECL/LVDS (no JAUX)|