32 Channel Multihit TDC (25 ps)
- 25 ps LSB
- 21 bit resolution
- 52 µs full scale range
- ECL/LVDS Input Signals
- 5 ns Double Hit Resolution
- Trigger Matching and Continuous Storage acquisition modes
- Leading and/or Trailing Edge detection
- 32 k x 32 bit output buffer
- MBLT, CBLT and 2eSST data transfer
- Multicast commands
- Live Insertion
- Libraries, Demos (C and LabView) and Software tools for Windows and Linux
The V1290A-2eSST is a 32 channel Multihit TDC, housed in a 1-unit wide VME 6U module. The unit features High Performance Time to Digital Converter chips developed by CERN. LSB is 25 ps (21 bit resolution, 52 µs FSR). The module accepts both ECL and LVDS inputs.
The channels can be enabled for the detection of hits rising/falling edges. For each channel there is a digital adjustment for the zero-ing of any offsets. The data acquisition can be programmed in “Events” (“Trigger Matching Mode”, with a programmable time window) or in “Continuous Storage Mode”.
The module programming is performed via a microcontroller that implements a high-level user friendly interface. The VME interface allows the module to work in A24 and A32 addressing modes.
The board houses a 32 k x 32 bit deep Output Buffer, that can be readout via VME in a completely independent way from the acquisition itself.
The device supports MBLT, CBLT and 2eSST readout modes. Live insertion is also supported.
32 Channel Multihit TDC (25 ps)Product page
|Name||File extension||File size||Revision||Date|
|V1190_REV_1.1.RBF||RBF||163.05 kB||1.1||February 10th, 2016|
|Name||File extension||File size||Revision||Last update|
|V1290/VX1290||2.37 MB||16||November 29th, 2016|
|High Performance Time to Digital Converter v2.2 User Manual (for HPTDC version 1.3)||1.23 MB||2||March 1st, 2004|
|Precautions for Handling Storage Installation (ENG/ITA)||179.29 kB||-||April 10th, 2019|
Compare with TDCs.
|WV1290AEXAAE||V1290A - 2ESST 32 Ch. Multievent Multihit TDC 25 psec ECL/LVDS (no JAUX)|