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V1290A-2eSST

32 Channel Multihit TDC (25 ps)

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Features

  • 25 ps LSB
  • 21 bit resolution
  • 52 µs full scale range
  • ECL/LVDS Input Signals
  • 5 ns Double Hit Resolution
  • Trigger Matching and Continuous Storage acquisition modes
  • Leading and/or Trailing Edge detection
  • 32 k x 32 bit output buffer
  • MBLT, CBLT and 2eSST data transfer
  • Multicast commands
  • Live Insertion
More info
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Overview

The CAEN Mod. V1290A-2eSST is a 32 channel Multihit TDC, housed in a 1-unit wide VME 6U module. The unit features High Performance Time to Digital Converter chips developed by CERN. LSB is 25 ps (21 bit resolution, 52 µs FSR). The module accepts both ECL and LVDS inputs.

The channels can be enabled for the detection of hits rising/falling edges. For each channel there is a digital adjustment for the zero-ing of any offsets. The data acquisition can be programmed in “Events” (“Trigger Matching Mode”, with a programmable time window) or in “Continuous Storage Mode”.
The module programming is performed via a microcontroller that implements a high-level user friendly interface. The VME interface allows the module to work in A24 and A32 addressing modes.

blank Header-type connector

Conn Header R/A 64pos 2.54mm for Mod. V1290A-2eSST

Consult our connectors reference page for technical information.

The board houses a 32 k x 32 bit deep Output Buffer, that can be readout via VME in a completely independent way from the acquisition itself.
The device supports MBLT, CBLT and 2eSST readout modes. Live insertion is also supported.

Technical Specifications

Packaging

6U-high, 1-unit wide, VMEx64X unit

Inputs

32 ECL / LVDS inputs, 110 Ohm impedance

Double hit resolution

5 ns

Acquisition modes

Trigger Matching Mode; Continuous Storage Mode

Built-in memory

32 kwords deep Output Buffer

LSB

25 ps

Dynamic Range

52 μs

RMS resolution (with compensation enabled)

35 ps (typical)

Integral non linearity (with compensation enabled)

<2.5 LSB

Max. differential non linearity (with compensation5 disabled)

<3 LSB

Interchannel Isolation

≤3 LSB

Offset spread

<2 ns6

EXT TRIGGER input

Two LEMO 00 bridged connectors, NIM signal, 50 Ohm

Double Trigger resolution

75 ns

Clock source

Internal (40 MHz) or External (on Control connector), dip switch selectable

Control inputs

active-high, differential ECL input signals:
CLR: performs the Hardware CLEAR (min. width: 25 ns)
rising-edge active, differential ECL input signals:
CRST: performs the Bunch RESET (min. width: 25 ns)
CLK: external clock (max. freq.: 40 MHz)
TRG: trigger for the TDC latching (min. width: 25 ns)

Control outputs

differential ECL output signal:
OUT_PROG: control output signal, programmable via the
out prog control register

Displays

DTACK: green LED; lights up at each VME access.
PWR: green/red LED; green: power ON, red: failure status.
TERM: green LED; control bus termination ON.
FULL: red LED; memory full.
ERROR: red LED; TDC global error.
DRDY: yellow LED; at least one datum/event in the Output Buffer

VME

Addressing modes: A24, A32, MCST
Data modes: D16, D32, MBLT32, BLT64, CBLT32, CBLT64, 2eVME, 2eSST7
Readout rate: up to 120 Mbyte/s with 2eSST

Compare

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Accessories

A954
Cable assembly 2.54mm 34 pin female to two 2.54mm 16 pin female - 50 cm

Ordering Options

Code Description
WV1290AEXAAE V1290A - 2ESST 32 Ch. Multievent Multihit TDC 25 psec ECL/LVDS (no JAUX)  

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