A5205
64 Channel Psiroc unit for FERS-5200
Features
- 64-channel readout with Weeroc Psiroc ASIC
- Triggering down to 0.5 fC for sub-20 pF detectors
- Dual-gain charge measurement and ToT output
- Sub-ns timing resolution with picoTDC (3.125 ps LSB)
- Positive/negative input polarity supported
- Adjustable gain up to 4 V/pC, shaping from 20 ns to 3 μs
- Low dead time acquisition without multiplexed ADC
- Fully supported by Janus 5205 software suite
Overview
The module A5205 is a detector readout board suited for PIN diodes, silicon strips and GEMs, handling detector capacitances ranging from 0 up to few hundreds of pF. The module is part of the FERS-5200 family, a Front-End Readout System designed for the readout of large detector arrays such as SiPMs, multi-anode PMTs, Silicon Strip detectors, Wire Chambers, GEM, Gas Tubes and others. FERS is a distributed and scalable system, where each unit is a small card that houses 64 or 128 channels. It features a detector specific Front-End interfaced to a common infrastructure that guarantees readout interfaces, slow control and synchronization. Typically, the front-end is based on ASIC chips that allow for high density, cost effective integration of multi-channel readout electronics into small size and low power modules. FERS is a flexible platform: combining the same back-end (i.e. readout architecture and interface) with different types of front-end to fit a wide range of detectors.
The front end electronics of the A5205 (and DT5205, which is the boxed version for desktop use) is based on the Psiroc chip (produced by Weeroc), that includes a Charge Sensitive Preamplifier (CSP), followed by 2 slow shapers (high and low gain) for the peak sensing ADC and 1 fast shaper for the discriminators that provide triggers and timing information. The individual channel triggers are connected to the FPGA, for hit counting and for triggering, and to a picoTDC, an ASIC chip produced by CERN, implementing a 64 channel TDC with LSB = 12.5 ps, for very precise timing measurements. Time Over Threshold (ToT) can also be used to estimate the pulse height, making it possible to acquire time stamp and PHA with very low dead time and extremely high rate, without the need of the multiplexed A/D conversion.
The most relevant A5205 acquisition modes are:
- Spectroscopy Mode: in this mode, the acquisition is simultaneous for the 64 channels of the board. The analog chain made of pre-amplifier (both High and Low gain), shaper and peak sensing is used to acquire the PHA with high energy resolution and wide dynamic range. The common trigger, that initiates the A/D conversion through the multiplexed outputs, can be generated by a combination of the channel self-triggers or from an external signal received from the T0 or T1 inputs. In parallel to the ADC data for the PHA, it is also possible to get high resolution timing information from the picoTDC that receives the individual channel triggers. The event data packet is therefore composed by the common trigger time stamp, trigger ID, dual PHA information (High and Low gains, optionally zero suppressed), individual arrival time of the channel hits that fall in the acquisition window open by the trigger. In spectroscopy mode, after each trigger, there is a dead-time due to the multiplexed A/D conversion. The amount of dead-time is of the order of 30 us, although it depends on the configuration.
- Counting Mode: the purpose of this acquisition mode is to count the number of self-triggers (i.e. input pulses) of each channel in a time window of programmable size (dwell time). The internal memory buffers allow for saving the channel counts of consecutive time windows, thus implementing a Multi Channel Scaler (MCS) with 64 inputs. The counting mode can also be used to generate the trigger efficiency curves (i.e. counts as a function of the trigger threshold). Looking at these curves, it is possible to define the “zero” of the signal (offset), the minimum threshold above the noise as well as the size of the DAC LSB reported to the input range of the signal.
- Timing Mode: in timing mode, the peak ADC is disabled and the readout data are only those ones coming from the picoTDC. It is possible to acquire the ToA (Time of Arrival) and/or the ToT (Time over Threshold) of the input pulses. In timing mode, there is no dead-time due to the A/D conversion and there is no need of a common trigger, since the 64 channels are independent and can acquire data in streaming mode, just using their self-triggers (trigger-less acquisition). The ToT can be used to estimate the pulse charge with 1% linearity energy measurement up to 100 pC.
The timing mode has 2 different options:- Trigger Matching: in this mode, there is a trigger signal that defines an acquisition window with arbitrary width and position with respect to the trigger. Only the hits belonging to that window will be recorded. Multiple hits on the same channels will be recorded, as far as there is space in the memory buffers. The acquisition trigger
can be a combination of the channel self-triggers or an external signal connected to the T0/T1 inputs. - Streaming Timing Mode: this acquisition mode implements a continuous hit recording, without any gate or trigger windowing. All hits received by the inputs are time stamped (56 bit) and saved in the form of a sorted list, along with ToT if enabled.
- Trigger Matching: in this mode, there is a trigger signal that defines an acquisition window with arbitrary width and position with respect to the trigger. Only the hits belonging to that window will be recorded. Multiple hits on the same channels will be recorded, as far as there is space in the memory buffers. The acquisition trigger
Technical Specifications
- MECHANICAL
Weight Dimension t.b.d. 72.8 W x 22.0 H x 208.5 L mm3
- INPUTS
64 channels
Input edge connector type Samtec HSEC8-170. Mating connector: Samtec HSEC8-170-01-S-DVSignal polarity: Positive or negative
Input impedance: t.b.d. (there is no termination, Zin is the one of the Psiroc chip)
Each input has two pins: Signal from detector and GND
- SPECTROSCOPY
SENSITIVITY
(CSP GAIN)Min = 125 mV/pC, Max = 4 V/pC, 64 steps (1 step = 125 mV/pC)
CSP is followed by two slow shapers with different gainsSHAPING TIME Short Range: Min = 20 ns, Max = 300 ns, 16 steps (1 step = 20 ns)
Long Range: Min = 200 ns, Max = 3000 ns, 16 steps (1 step = 200 ns)ADC Energy Histograms can be 256, 512, 1k, 2k, 4k and 8k channels FSR @ 125 mV/pC: HG = t.b.d.; LG = t.b.d.
FSR @ 4 V/pC: HG = t.b.d.; LG = t.b.d.DYNAMIC RANGE Up to 5 pC
- TIMING & COUNTING
SELF-TRIGGERS Dedicated fast preamps + discriminator for input pulse self-triggering. Trigger threshold down to 0.5 fC.
Discriminators: two branches: ToA with fast shaper and ToT direct from CSP
Thresholds: common 10 bit DAC + individual 4 bit DACTIMING
RESOLUTION155 ps RMS @ Qin = 4 fC
Time Stamp Range: 64 bit
Intrinsic timing resolution of picoTDC = 12.5 ps LSBTOT Time over Threshold (ToT): indirect charge measurement up to 100 pC. COUNTING t.b.d.
MCS mode with programmable dwell time: from 16 ns to ~34 s
- TRIGGER LOGIC
Global trigger common to 64 channels: used in Spectroscopy mode to start Peak acquisition, in Timing mode to generate the acquisition windows (Gate). Trigger-less acquisition in Timing Streaming mode.
Global Trigger Sources:
- OR of self-triggers = OR(0..63)
- Plane coincidence: OR(0..31) AND OR(32..63)
- Paired channels: AND(0..1) OR AND(2..3) … OR AND(62..63)
- Majority with programmable threshold
- External trigger (T0-IN, T1-IN, LEMO, TTL/NIM)
- Internal periodic trigger with programmable frequency
- SYNCHRONIZATION
Acquisition Trigger Time Stamp: 56 bit, step = 12.8 ns.
Two synchronization modes:- T0 or T1 IN-OUT daisy chain: max jitter = 100 ns
- Fiber optic (TDlink) and DT5215 Concentrator: up to 128 boards, max jitter 50 ps
- INPUT ADAPTERS
A5250: two 35×2, 2.54 mm male header connectors
A5253: 64+1 individual 3 pin, AMPMODU type 3-102203-4 connectorsBy default, the desktop version DT5205 comes with an A5250 as a front panel.
- FRONT PANEL I/Os
T0-IN, T1-IN: LEMO-00 connector, NIM or TTL (terminated to 50 Ω) T0-OUT, T1-OUT: LEMO-00 connector, TTL (50 Ω termination required) SW selectable IN-OUT bypass and termination removal for daisy chaining
Functions (SW programmable): Trigger, Acquisition Start/Stop, Sync, Busy, Veto, Signal inspection, etc…
- FRONT PANEL LEDs
GREEN: Power-ON, Init-Done, Run, Trigger, Data Ready, T0-IN, T1-IN ORANGE: Event Overrun (rejected triggers because received while busy)
RED: Failure (missing clock, over-temperature, etc…)
- INTERNAL PULSER
Psiroc provides a test input pin that can be internally connected to the pre-amplifier inputs, channel by channel. The test signal can come from an external signal (MCX connector on the PCB) or generated by an internal pulser with programmable amplitude. The internal pulser can be trigger by T0/T1 IN or by the internal periodic trigger.
- ACQUISITION MODES
Spectroscopy: The common trigger initiates the peak sensing detection and A/D conversion (13 bit) on all channels simultaneously. Conversion time = ~30 μs. Output Data: Trigger time stamp, Trigger ID, PHA (Low and/or High Gain). Zero suppression with programmable threshold. Counting: 32 bit counters. Common trigger defines dwell time (i.e. counting window). No dead-time between subsequent windows. Internal period trigger from 16 ns to ~34 s. Output Data: Trigger time stamp, Trigger ID, channel counts. Zero suppression available. Counters are automatically reset after each trigger.
Timing (Trigger Matching): The common trigger signal defines an acquisition window with programmable width and offset. All hits falling into the window will be recorded. Multi-hit acquisition is supported. Output Data: Trigger time stamp, Trigger ID, ToA or ToA+ToT
Timing (Streaming): continuous hit recording, without any gate or trigger windowing. All hit time measurements are expressed as 64 bit time stamps and saved in the form of a sorted list. Output Data: ToA or ToA+ToT
- COMMUNICATION INTERFACES
USB Ethernet Optical Link USB2.0: microUSB connector Bandwidth = ∼ 3 MB/s
Ethernet connector, type Rj-45. Supports 10/100 Mbit/s connection to a PC Bandwidth = ∼ 2.5 MB/s
Small Form Factor Pluggable (SFP+) transceiver component for optical connection (3.125 Gbit/s). TDlink CAEN proprietary protocol allows for multi-board synchronization, slow control and data readout
Data Concentrator DT5215 required
- POWER
power supply voltage: +12 V (min = +7V, max = +15V) power consumption: t.b.d.
110V/220V AC/DC converter provided with Desktop version only.
- FIRMWARE
Firmware of FPGA be upgraded via USB, Ethernet or Optical Link Firmware of μC can be upgraded via Ethernet only
- SOFTWARE
Readout SW
Fully controlled by the Janus 5205 open source software for Windows® and Linux®.
It can run in console mode (C program, with console commands and gnuplot display for plots) or connected to a GUI (Python) that implements user friendly configuration panels and run controls.Janus 5205 can perform multiple board acquisition of PHA energy spectrum (Low and High Gain), ToT spectrum (represents PHA in timing mode), ΔT spectrum, with event building based on trigger ID or time stamp.
Live Display: channel hit count and rate, trigger rate, lost triggers, data throughput, acq. time, etc…
Plots: PHA, ΔT, ToT, hit rate, 2-D heat map with channel hit rates or PHA.
Threshold calibration curves via threshold scan (counts vs threshold)
Output Files: histograms (spectra), list files (PHA, ToA, ToT, ΔT), Run Info, Sync file.
Web Interface
Board information and monitoring, Ethernet configuration.
Compare
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Ordering Options
| Code | Description |
|---|---|
| WA5205XAAAAA | A5205 - 64 channel Psiroc unit for FERS-5200 with picoTDC RoHS |
