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VX1190A-2eSST

128 Channel Multihit TDC (100/200/800 ps)

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Features

  • 3 programmable ranges: 100 ps LSB (19 bit resolution), 200 ps LSB (19 bit) and 800 ps LSB (17 bit)
  • ECL/LVDS inputs automatically detected
  • 5 ns Double Hit Resolution
  • Leading and Trailing Edge detection
  • Trigger Matching and Continuous Storage acquisition modes
  • 32 k x 32 bit output buffer
  • MBLT, CBLT and 2eSST data transfer
  • Multicast commands
  • Geopraphical address supported
  • Live insertion
  • Libraries, Demos (C and LabView) and Software tools for Windows and Linux
More info
3 Years Warranty
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Overview

The CAEN Mod. VX1190A-2eSST is a 128 channel Multihit TDC, housed in a 1-unit wide VME64X 6U module. The unit features High Performance Time to Digital Converter chips developed by CERN. LSB can be set at 100 ps (19 bit resolution, 52 µs FSR), 200 ps (19 bit, 104 µs FSR) or 800 ps (17 bit, 104 µs FSR).

The channels can be enabled for the detection of hits rising/falling edges or for their width measurement (both the edges’ timing, and the hit width can be measured with the selected resolution). For each channel there is a digital adjustment for the zero-ing of any offsets. The data acquisition can be programmed in “Events” (“Trigger Matching Mode”, with a programmable time window) or in “Continuous Storage Mode”. Both ECL and LVDS input signals are supported. The module programming is performed via a microcontroller that implements a high-level user friendly interface. The VME interface allows the module to work in A24 and A32 addressing modes.
The board houses a 32 k x 32 bit deep Output Buffer that can be readout via VME in a completely independent way from the acquisition itself.

The device supports MBLT, CBLT and 2eSST readout modes. Live insertion is also supported.

Technical Specifications

Packaging

6U-high, 1-unit wide, VMEx64X unit

Inputs

128 ECL/LVDS inputs, 110 Ω impedance

Acquisition modes

Trigger Matching Mode, Continuous Storage Mode

Double hit resolution

5 ns

Built-in memory

32 kwords deep Output Buffer

LSB

VME programmable: 100 / 200 / 800 ps

Dynamic Range

104 μs (200 ps and 800 ps LSB); 52 μs (100 ps LSB)

RMS resolution (with compensation enabled)
  • <320 ps @ 800 ps res.
  • <140 ps @ 200 ps res.
  • <80 ps @ 100 ps res.
Integral non linearity (with compensation enabled)
  • <0.3 LSB @ 800 ps res.
  • <1 LSB @ 200 ps res.
  • <1 LSB @ 100 ps res.
Max. differential non linearity (with compensation disabled)
  • <0.2 LSB @ 800 ps res.
  • <0.3 LSB @ 200 ps res.
  • <0.5 LSB @ 100 ps res.
Interchannel Isolation

≤0.7 LSB

Offset spread

<2 ns7

EXT TRIGGER input

Two LEMO 00 bridged connectors, NIM signal, 50 Ohm

Double Trigger resolution

75 ns

Clock source

Internal (40 MHz) or External (on Control connector), dip switch selectable Control inputs active-high, differential ECL input signals:
CLR: performs the Hardware CLEAR (min. width: 25 ns)
rising-edge active, differential ECL input signals:

Control inputs
  • CRST: performs the Bunch RESET (min. width: 25 ns)
  • CLK: external clock (max. freq.: 40 MHz)
  • TRG: trigger for the TDC latching (min. width: 25 ns)
    L2_A; L2_REJ
Displays
  • DTACK: green LED; lights up at each VME access.
  • PWR: green/red LED; green: power ON, red: failure status.
  • TERM: green LED; control bus termination ON.
  • FULL: red LED; memory full.
  • ERROR: red LED; TDC global error.
  • DRDY: yellow LED; at least one datum/event in the Output Buffer
VME
  • Addressing modes: A24, A32, MCST
  • Data modes: D16, D32, MBLT32, BLT64, CBLT32, CBLT64, 2eVME, 2eSST8
  • Readout rate: up to 120 Mbyte/s with 2eSST

Compare

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Accessories

A967
Cable assembly 68 pin P50 to two 2.54mm 34 pin male - 25 cm
A966
Cable assembly 68 pin P50 to four 2.54mm 16 pin male - 25 cm

Ordering Options

Code Description
WVX1190AEXAE VX1190A - 2ESST 128 Ch. Multievent Multihit TDC 100-200-800 psec ECL/LVDS (no JAUX)  

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