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128 channels, 14-bit @125 MS/s Digitizer
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Based on powerful Xilinx Zynq-7000 SoC with open FPGA
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2U, 19” Rackmount unit with automatic fan control
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Full-featured readout system for the readout of large arrays of detector (PMTs, segmented HPGe, Gas Tubes, …)
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Specifically designed for the readout of position-sensitive 3He tubes in combination with R1443 preamplifier
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2 Vpp input dynamic
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Fully supported by SCI-Compiler for easy FPGA programming (Firmware runtime license included onboard)
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Easily scalable
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Board-to-board synchronization with a single CAT5e cable.
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Configurable digital I/Os to interface with external systems
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Maximum flexibility: USB3.0, Ethernet, and Optical Link (OPTIONAL) connectivity, to support remote management as well as extreme fast data flow
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2.4” touch screen display for quick configuration and status control
The R5560 is a 2U, 19″ rack-mount 128 Channels 14-bit 125MS/s Open FPGA Digitizer Family, designed to attain programmable data processing capabilities.
The R5560 is designed for the readout of large arrays of detectors (PMTs, segmented HPGe, 3He tubes, …) using a customizable platform. In fact, it is possible to take advantage of the powerful SoC mounted onboard to write a custom pulse processing algorithm on the open FPGA as well as build a middleware/software that fits the needs of the application of interest.
The board can manage simultaneously a large number of digital (LVDS, NIM, TTL) and analog signals, allowing to implement many functionalities required by physics experiments: signal digitization, complex trigger logic, Pulse Height Analysis with MCA capabilities, Time Tagging, Pulse Shape Discrimination, etc.
It is an optimal solution for large experiments, usually requiring fast digitization of analog signals and usage of several digital lines to interface with external systems. The board supports multi-board synchronization through a single CAT5e cable, with the possibility scale up to thousands of channels. Moreover, the rack-mount form factor simplifies the experimental setup in case of multi-board systems, where an effective space management is often a constraint. The usage of differential inputs on RJ45 connectors optimizes the cost for the installation, reducing the cabling cost.
SCI-Compiler software, the CAEN block-diagram-based firmware generator and compiler, helps in programming the FPGA to develop intensive real-time data processing. A free and open-source demo readout software is available to manage the standard pulse height analysis firmware implementing energy measurements using a trapezoidal filter.
Applications includes:
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Readout of the following detectors |
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Readout of mixed signals ASICs |
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Nuclear Spectroscopy |
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High Energy Physics |
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Imaging with multichannel detectors |
Developed in collaboration with Nuclear Instruments.
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Technical Specifications
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General |
Form Factor : 19”, 2U Rack-mount |
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Power Requirements |
Voltage: 100-240 Vac |
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Analog Input |
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Digital Input |
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Digital Conversion |
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Clock Generation |
Clock source: internal/external |
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LEMO Digital I/O |
USER IO 0…5 (LEMO)
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Trigger |
Trigger Source: Internal/External: managed by the default firmware; Complex trigger logic: implementable by the user on the open FPGA. |
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Open FPGA |
4x Xilinx Zynq-7000 SoC: |
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Memory |
1 GByte of memory for list readout on each SoC |
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Communication Interface |
All readout interfaces allow to perform the same task at different speed and using different media. They can be used independently or simultaneously.
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Firmware |
Default: Waveform recording and Pulse Height Analysis, Ethernet communication |
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Firmware Upgrade |
Firmware can be upgraded via Ethernet, USB 3.0 or USB 2.0 debugger (on-fly) |
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Software |
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