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GEMROC 1

New

Micromegas and GEMs semi digital read out chip

  • TRL Technology Readiness Level 9 – Full system running, reliability proven
  • Detector Read-Out Micromegas, GEM
  • Number of Channel 64
  • Signal Polarity Negative
  • Sensitivity Trigger on 1 fC with 100% efficiency

Overview

GEMROC 1 is a 64-channel front-end ASIC designed to readout negative fast (<1ns) and short (<10ns) current pulses from low gain detectors (GEMs, Micromegas, …). GEMROC 1 provides a semi-digital readout with three thresholds tunable from 1 fC to 500 fC and integrates a 128-deep digital memory to store the 2 x 64 discriminator outputs as well as the timestamp from a 24b counter. The three thresholds are set internally by three 10-bit DACs. The gain of each channel can be tuned individually from 0 to 2 over 8 bits, allowing the compensation of non-uniformity between the 64 detector channels. Each channel can auto trigger down to 1 fC input charge. A multiplexed charge measurement up to 500fC is integrated.
The power consumption is 1.5 mW/channel and the chip can be fully power-pulsed allowing a significant power reduction by disabling unused blocks.

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Code Description
WWGEMROC1QAA GEMROC 1 - Micromegas and GEMs semi digital read out chip - QFP (Quad Flat Pack) 

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