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DT5550W

Complete Readout System based on Weeroc ASIC

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Features

  • Comprehensive Programmable Board based on Weeroc ASICs
  • Available with Petiroc and Citiroc ASICs for SiPM Readout
  • Single Desktop Unit available in 32, 64, and 128-channel configurations
  • On-board Power Supply for SiPM Bias (20-85 V)
  • Cross-board synchronization for System-building and readout of large SiPM Arrays
  • Ideally suited for energy calculation in SiPM-based imaging and spectroscopy applications
  • Petiroc version is the perfect solution for highly accurate SiPM time-of-flight applications (Intrinsic 37ps timing resolution)
  • Strip adapter (2.54mm pitch) included for easy connection to any type of SiPM matrix or array
  • Optional remotization kit for Hamamatsu S13361-3050AE-08 64-channel SiPM matrix, with 2-meters microcoaxial cable
  • Open-FPGA Capability via Sci-Compiler software, a graphical development platform for quick, user-friendly FPGA programming
  • Includes SCI-5550W Readout Software (open source) for DAQ Management and ASIC Configuration
  • 80MS/s, 14bit ADC
  • Clock-In/Clock-Out (LEMO Connectors) for multi-board sync
  • 8 General Purpose Programmable I/O (LEMO Connectors) for DAQ Control Signals (external trigger, busy, veto, etc…)
  • USB 3.0 supports fast data transfer
More info
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Overview

The CAEN Mod.DT5550W is a development and DAQ platform with programmable FPGA designed to read out Weeroc ASICs. The DT5550W can be used either as evaluation system for WeeROC ASICs, either as full featured Acquisition System supporting a wide range of SiPM detectors.

The full system is composed by two boards: a motherboard with an FPGA, USB 3.0 connectivity, power supply and ADCs, and a replaceable piggyback board that hosts 1,2 or 4 WeeROC ASICs, detector connectors and SiPM bias power supply.

A default firmware is provided for each supported piggyback board, allowing the user to read-out the ASICs and perform energy and time measurements with the supported detectors.

The DT5550W is compatible with SCI-Compiler, a graphic tool for Windows which allows the user to realize a custom readout logic for the available ASICs. This tool allows to generate the VHDL firmware code starting only from graphical blocks which can be connected together in the GUI, thus reducing the development time also for non-expert firmware designers.

The following piggyback boards are available:

Piggyback board ASIC Optimal detectors Compatible detectors (not tested) Channels No.
A55PET4 4 x PETIROC2A SiPM, SiPM matrix RPCs 128
A55PET2 2 x PETIROC2A SiPM, SiPM matrix RPCs 64
A55PET1 1 x PETIROC2A SiPM RPCs 32
A55CIT4 4 x CITIROC1A SiPM, SiPM matrix / 128
A55CIT2 2 x CITIROC1A SiPM, SiPM matrix / 64

Piggyback Board
CAEN piggyback boards offer to the user the possibility to read out up to 128 SiPM detectors or two 64-channels SiPM matrices. The piggyback is equipped with CAEN A7585D HV module to bias all connected SiPMs. Up to 2 Hamamatsu matrices (S13361-3050AE-08 64 channels model) can be connected directly on the piggyback board, with the possibility to use an external adapter for any kind of matrix or array interfacing.
Developed in collaboration with blank

Technical Specifications

Form Factor

Desktop bare PCB

Dimensions (H/W/L)

24/152/260 mm3 (including the piggyback board and connectors)

Power Consumption

With A55PET4 piggyback 1A @ 12 V (Typ.)
With A55CIT4 piggyback 0.9A @ 12V (Typ.)

Analog Input
Channels: 32/64/128 (see ASIC datasheet for complete description of the analog stage)
Max. sustainable input rate: see A55xxxx User Manual
Bias Voltage

CAEN A7585D Power Supply for SiPM available on A55PETx and A55CITx piggyback

Digital Conversion

Internal ASIC ADC or external 80 MS/s, 14-bit ADC

Clock Generation
  • Clock source: internal/external
  • On-board programmable PLL provides generation of the main board clocks from an internal (25 MHz local Oscillator) or external (CLK-IN connector) reference
LEMO Digital I/O
CLOCK-IN (LEMO)
Zin = 50 Ω
Single-ended, 25 MHz, 3.3V
CLOCK-OUT (LEMO)
Rt = 50 Ω
Single-ended, 25 MHz, 3.3V, 50mA
 GPIO 1..8 (LEMO)
General purpose programmable digital I/Os Single-ended, Zin/ Rt= 50 Ω
Memory

Common FIFO buffer

Trigger

Trigger Source
Internal/External: managed by the default firmware Complex trigger logic: implementable by the user on the open FPGA

Trigger Propagation
Through programmable LEMO GPIO 1-8
Timing Resolution
Default FW
  • Digital Readout: refer to the ASIC datasheet
  • Analog Readout: 12.5 ns
  • Counting/TDC mode: 2 ns
Custom FW
  • Digital Readout: refer to the ASIC datasheet
Synchronization
Clock Propagation: LEMO CLOCK IN/OUT connectors
Acquisition Synchronization: Through programmable LEMO GPIO 1-8
FPGA

Open FPGA: Xilinx XC7K160T (Kintex-7 family)

Communication Interface

USB 3.0-typeB:

  • Up to 240 MB/s transfer rate
Firmware
Default: Basic ASICs readout
Custom: Use SCI-Compiler to develop your own firmware
Software
  • SCI-5550W Readout Software to manage the default firmware
  • SCI-Compiler for custom firmware development

Compare

Compare with Programmable DAQ Platforms.

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Ordering Options

Code Description
WDT5550WXAAA DT5550W - Weeroc ASICS Evaluation System   RoHS
WW55PETI2AA1 A55PET1 - Evaluation Board with 1 PETIROC chip   RoHS
WW55PETI2AA2 A55PET2 - Evaluation Board with 2 PETIROC chip   RoHS
WW55PETI2AA4 A55PET4 - Evaluation Board with 4 PETIROC chip   RoHS
WW55CITI1AA2 A55CIT2 - Evaluation Board with 2 CITIROC chip   RoHS
WW55CITI1AA4 A55CIT4 - Evaluation Board with 4 CITIROC chip   RoHS
WKREMOT5550W Remotization kit with 2-meters cable for DT5550W   RoHS

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