Logo Caen

VX1725 / VX1725S

16/8 Channel 14-bit 250 MS/s Digitizer

Request a quote
Downloads

Features

More info
placeholder

Overview

The VX1725S is a digitizer capable of recording waveforms along with performing advanced algorithms for online digital pulse processing (DPP). Utilizing DPP Firmware, users can acquire quantitative physical parameters (Integrated Charge, Pulse Shape Discrimination with very fine time resolution, Pulse Height Analysis) as well as read out waveforms with automatic pulse identification and baseline suppression on channel basis (Zero-Length Encoding and Dynamic Acquisition Window). The wide range of DPP algorithms supported by the VX1725S make it a “must-have” for any type of nuclear physics application.

The VX1725S (previously VX1725) has also been upgraded, introducing a larger FPGA to accommodate more complex DPP algorithms and a new A/D converter for better stability which does not require temperature-related calibration.

Input signals are read by a Flash ADC, 14-bit resolution and 250 MS/s sampling rate, which is well suited for mid-fast signals as the ones coming from liquid or inorganic scintillators coupled to PMTs or Silicon Photomultipliers, but also for high precision detectors as Silicon or HPGe coupled with charged sensitive preamplifiers. The acquisition can be channel independent and it is possible to make coincidence/ anti-coincidence logic among different channels and external veto/gating. Multiple boards can be synchronized to build up complex systems. In the case of DPP mode, data can be saved in time-stamped list mode to support higher input rates and improving the throughput performances. Piled-up events can be rejected or saved for oine analysis. The acquisition in DPP mode is fully controlled by the CoMPASS and MC2Analyzer software, which manage the algorithm parameters, build the plots and saves the relevant energy, time, and PSD spectra. In case of waveform recording mode, the user can take advantage of the CAENScope and WaveDump software to access and save the waveforms. Libraries and demo software in C and LabView are available for integration and customization of specific acquisition systems.

The VX1725S family comes in a VME64X form factor, with 16/8 input channels. The communication to and from the board is provided through the VMEBus and Optical Link interfaces.

Supported third-party software:

  • NSCLDAQ – National Superconducting Cyclotron Laboratory DAQ
  • FSUDAQ – Florida State University DAQ

Technical Specifications

GENERAL

Form Factor
1-unit wide, 6U VME64X

ANALOG INPUT
Channels
16/8 channels single ended

Impedance
50 Ω
Connector
MCX

Full Scale Range
0.5 or 2 Vpp
(SW selectable)
Bandwidth
125 MHz

Offset
Programmable DAC for DC offset adjustment in the full scale range
DIGITAL CONVERSION
Resolution
14 bits
Sampling Rate
250 MS/s
Simultaneously on each channel
SYSTEM PERFORMANCES

VX1725 / VX1725S Baseline RMS Noise (open inputs)
@ 2 Vpp: 2.6 LSB = 312 uV
@ 0.5 Vpp: 3.4 LSB = 102 uV

ADC CLOCK GENERATION

Clock source: internal/external
Onboard programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference

DIGITAL I/O
CLK-IN (AMP Modu II)
AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by CAEN adapter)
Jitter < 100ppm requested

CLK-OUT (AMP Modu II)
DC coupled LVDS output clock for multi-board synchronization
TRG-OUT (LEMO)
Local trigger digital output
NIM/TTL, Rt = 50 Ω



TRG-IN (LEMO)
External trigger digital input
NIM/TTL, Zin = 50 Ω
S-IN (LEMO)
SYNC/START front panel digital input
NIM/TTL, Zin = 50 Ω
ACQUISITION MEMORY
  • 640 kS/ch (2.5 ms @ 250 MS/s) or 5.12 MS/ch (20 ms @ 250 MS/s) Multi-event Buffer divisible into 1 ÷ 1024 buffers
  • Independent read and write access
  • Programmable event size and pre/post-trigger
TRIGGER
Trigger Source
Self-trigger: channel over/under threshold for either Common or Individual (DPP only) trigger generation
External-trigger: Common by TRG-IN connector
Software-trigger: Common by software command

Trigger Propagation
GPO digital output
Trigger Time Stamp
Waveform Recording: 31-bit counter, 16 ns resolution, 17 s range; 48-bit extension by firmware
DPP-PSD: 47-bit counter, 4 ns resolution, 156 h range; 10-bit and 4 ps fine time stamp with digital CFD
DPP-PHA: 47-bit counter, 4 ns resolution, 156 h range
DPP-DAW: 48-bit counter, 4 ns resolution, 312 h range
DPP-ZLEplus: 48-bit counter, 32 ns resolution, 1250 h range
SYNCHRONIZATION
Clock Propagation
Daisy chain: CLK-IN/CLK-OUT connectors
One-to-many: clock distribution from DT4700 on CLK-IN connector
Clock Cable delay compensation
Acquisition Synchronization
Sync Start/Stop through digital I/O (S-IN or TRG-IN input, TRG-OUT output)
Trigger Time Stamp Alignment
By S-IN input connector
ADC & MEMORY CONTROLLER FPGA
x725
Altera Cyclone EP4CE30
(one FPGA serves 4 channels)
x725S
Intel/Altera Arria V GX
(one FPGA serves 4 channels)
ANALOG MONITOR
  • 12-bit/125 MHz DAC FPGA controlled output with four operating modes:
  • Test pulses: 1 Vpp ramp generator
  • Majority signal: proportional to the no. of channels under/over the threshold (steps of 125 mV)
  • Memory Occupancy signal: proportional to the Multi-Event Buffer Occupancy (1 buffer ~ 1mV)
  • Voltage level: programmable output voltage level
LVDS I/O
  • 16 general purpose LVDS I/Os controlled by FPGA
  • Busy, Data Ready, Memory Full, Individual Trg-Out and other functions can be programmed
  • An Input Pattern from the LVDS I/Os can be associated to each trigger as an event marker
COMMUNICATION INTERFACE
VME
VME 64X compliant
Data transfer mode: BLT32, MBLT64 (70 MB/s using CAEN Bridge), CBLT32/64, 2eVME, 2eSST (up to 200 MB/s)
Optical Link
CAEN CONET proprietary protocol, up to 80 MB/s transfer rate
Daisy chainable: it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod.A2818/A3818)
FIRMWARE
Waveform Recording Firmware
Free firmware for waveform recording

Upgrades
Firmware can be upgraded via Optical Link or VMEBus
DPP Firmware
Paid firmware for Digital Pulse Processing: DPP-PSD, DPP-PHA, DPP-ZLEplus, and DPP-DAW
POWER CONSUMPTIONS

VX1725: 5.2 A @ +5 V; 750 mA @ +12 V; -12 V not used
VX1725S: 7.5 A @ +5 V; 700 mA @ +12 V; -12 V not used
VX1725SB: 8 A @+5V; 800 mA @+12V; 400 mA @-12V (ref. PCB rev. 0)
VX1725SC: 5 A @+5V; 500 mA @+12V; -400 mA @-12V (ref. PCB rev. 0)
VXV1725B/1725C/1725D: n.a.
VX1725SD: 6.5 A @ +5 V; 500 mA @ +12 V; -12 V not used

Compare

Compare with Digitizers.

Loading...

Accessories

AI2700
Optical Fiber Series
A654
Cable assembly LEMO 00 male to MCX male – 1 m
A659
Cable assembly BNC male to MCX male – 1 m
A317
Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm
A318
Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
A316
Cable assembly 2.54mm 2-pin header female - 5 cm
A952
Cable assembly 2.54mm 34 pin female to 2.54mm 34 pin female - 50 cm
A953
Cable assembly 2.54mm 34 pin female to two 2.54mm 34 pin female – 50 cm
A954
Cable assembly 2.54mm 34 pin female to two 2.54mm 16 pin female - 50 cm

Ordering Options

Code Description
WVX1725BXAAA VX1725B - 16 Ch. 14 bit 250 MS/s Digitizer: 5.12MSch, CE30, SE  (Obsolete) RoHS
WVX1725CXAAA VX1725C - 8 Ch. 14 bit 250 MS/s Digitizer: 640kS/c, CE30, SE  (Obsolete) RoHS
WVX1725DXAAA VX1725D - 8 Ch. 14 bit 250 MS/s Digitizer: 5.12MS/ch, CE30, SE  (Obsolete) RoHS
WVX1725XAAAA VX1725 - 16 Ch. 14 bit 250 MS/s Digitizer: 640kS/ch, CE30, SE  (Obsolete) RoHS
WVX1725SBXAA VX1725SB - 16 Ch. 14 bit 250 MS/s Digitizer: 5.12MSch, Arria V GX, SE   RoHS
WVX1725SCXAA VX1725SC - 8 Ch. 14 bit 250 MS/s Digitizer: 640kS/c, Arria V GX, SE   RoHS
WVX1725SDXAA VX1725SD - 8 Ch. 14 bit 250 MS/s Digitizer: 5.12MS/ch, Arria V GX, SE   RoHS
WVX1725SXAAA VX1725S - 16 Ch. 14 bit 250 MS/s Digitizer: 640kS/ch, Arria V GX, SE   RoHS

Need more help? Talk to us

Products promotions

Contacts

Great to have you back!

Forgotten password?
New Here? Create a MyCAEN account.