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N6725 / N6725S

8 Channel 14-bit 250 MS/s Digitizer

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Overview

The CAEN Mod.N6725S is a digitizer capable of recording waveforms along with performing advanced algorithms for online digital pulse processing (DPP).  Utilizing DPP Firmware, users can acquire quantitative physical parameters (Integrated Charge, Pulse Shape Discrimination with very fine time resolution, Pulse Height Analysis) as well as read out waveforms with automatic pulse identification and baseline suppression on channel basis (Zero-Length Encoding and Dynamic Acquisition Window). The wide range of DPP algorithms supported by the N6725S make it a “must-have” for any type of nuclear physics application.

The N6725S (previously N6725) has also been upgraded, introducing a larger FPGA to accommodate more complex DPP algorithms and a new A/D converter for better stability which does not require temperature-related calibration.

Input signals are read by a Flash ADC, 14-bit resolution and 250 MS/s sampling rate, which is well suited for mid-fast signals as the ones coming from liquid or inorganic scintillators coupled to PMTs or Silicon Photomultipliers, but also for high precision detectors as Silicon or HPGe coupled with charged sensitive preamplifiers. The acquisition can be channel independent and it is possible to make coincidence / anti-coincidence logic among different channels and external veto/gating. Multiple boards can be synchronized to build up complex systems. In the case of DPP mode, data can be saved in time-stamped list mode to support higher input rates and improving the throughput performances. Piled-up events can be rejected or saved for oine analysis. The acquisition in DPP mode is fully controlled by the CoMPASS and MC2Analyzer software, which manage the algorithm parameters, build the plots and saves the relevant energy, time, and PSD spectra. In case of waveform recording mode, the user can take advantage of the CAENScope and WaveDump software to access and save the waveforms. Libraries and demo software in C and LabView are available for integration and customization of specific acquisition systems.

The N6725S family comes in a NIM form factor, with 8 input channels. The communication to and from the board is provided through the USB and Optical Link interfaces.

Supported third-party software:

  • NSCLDAQ – National Superconducting Cyclotron Laboratory DAQ
  • FSUDAQ – Florida State University DAQ

Technical Specifications

GENERAL

Form Factor
1-unit wide NIM

ANALOG INPUT
Channels
8 channels single ended

Impedance
50 Ω
Connector
MCX

Full Scale Range
0.5 or 2 Vpp
(SW selectable)
Bandwidth
125 MHz

Offset
Programmable DAC for DC offset adjustment in the full scale range
DIGITAL CONVERSION
Resolution
14 bits
Sampling Rate
250 MS/s
Simultaneously on each channel
SYSTEM PERFORMANCES

N6725 / N6725S Baseline RMS Noise (open inputs)
@ 2 Vpp: 2.6 LSB = 312 uV
@ 0.5 Vpp: 3.4 LSB = 102 uV

ADC CLOCK GENERATION

Clock source: internal/external
Onboard programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference

DIGITAL I/O
CLK-IN (AMP Modu II)
AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by CAEN adapter)
Jitter < 100 ppm requested
GPO (LEMO)
General purpose digital output
NIM/TTL, Rt = 50 Ω

GPI (LEMO)
General purpose digital input
NIM/TTL, Zin = 50 Ω
TRG-IN (LEMO)
External trigger digital input
NIM/TTL, Zin = 50 Ω
ACQUISITION MEMORY

640 kS/ch (2.5 ms @ 250 MS/s) or 5.12 MS/ch (20 ms @ 250 MS/s) Multi-event Buffer divisible into 1 ÷ 1024 buffers
Independent read and write access.
Programmable event size and pre/post-trigger.

TRIGGER
Trigger Source
– Self-trigger: channel over/under threshold for either Common or Individual (DPP only) trigger generation
– External-trigger: Common by TRG-IN connector
– Software-trigger: Common by software command

Trigger Propagation
GPO digital output
Trigger Time Stamp
– Waveform Recording: 31-bit counter, 16 ns resolution, 17 s range; 48-bit extension by firmware
– DPP-PSD: 47-bit counter, 4 ns resolution, 156 h range; 10-bit and 4 ps fine time stamp with digital CFD
– DPP-PHA: 47-bit counter, 4 ns resolution, 156 h range
– DPP-DAW: 48-bit counter, 4 ns resolution, 312 h range
– DPP-ZLEplus: 48-bit counter, 32 ns resolution, 1250 h range
SYNCHRONIZATION
Clock Propagation
One-to-many: clock distribution from DT4700 to CLK-IN connector
Acquisition Synchronization
Sync Start/Stop through digital I/O (TRG-IN input, GPO output)
Trigger Time Stamp Alignment
By GPI input connector
ADC & MEMORY CONTROLLER FPGA
N6725
Altera Cyclone EP4CE30
(one FPGA serves 4 channels)
N6725S
Intel/Altera Arria V GX
(one FPGA serves 4 channels)
COMMUNICATION INTERFACE
USB
USB 2.0 compliant
Transfer rate up to 30 MB/s
Optical Link
CAEN CONET proprietary protocol, up to 80 MB/s transfer rate
Daisy chainable: it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod. A4818/A3818)
FIRMWARE
Waveform Recording Firmware
Free firmware for waveform recording

Upgrades
Firmware can be upgraded via Optical Link or USB
DPP Firmware
Paid firmware for Digital Pulse Processing: DPP-PSD, DPP-PHA, DPP-ZLEplus, and DPP-DAW
POWER CONSUMPTIONS
N6725
5 A @ +6 V
300 mA @ -6 V		 N6725S
3.5A @ +6V
200 mA @ -6V		 N6725SB
6.5A @ +6V
200 mA @ -6V

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Accessories

A654
Cable assembly LEMO 00 male to MCX male – 1 m
A659
Cable assembly BNC male to MCX male – 1 m
AI2700
Optical Fiber Series
A318
Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
A317
Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm

Ordering Options

Code Description
WN6725BXAAAA N6725B - 8 Ch. 14 bit 250 MS/s Digitizer: 5.12MS/ch, CE30, SE  (Obsolete) RoHS
WN6725XAAAAA N6725 - 8 Ch. 14 bit 250 MS/s Digitizer: 640kS/ch, CE30, SE  (Obsolete) RoHS
WN6725SBXAAA N6725SB - 8 Ch. 14 bit 250 MS/s Digitizer: 5.12MS/ch, Arria V GX, SE   RoHS
WN6725SXAAAA N6725S - 8 Ch. 14 bit 250 MS/s Digitizer: 640kS/ch, Arria V GX, SE   RoHS

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