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DT5724

2/4 Channel 14 bit 100 MS/s Digitizer

Features

Overview

The CAEN Mod. DT5724 is a digitizer able to record waveforms along with performing advanced algorithms for online digital pulse processing (DPP) of pulse height analysis and dynamic acquisition window.

Data is read by a Flash ADC, 14-bit resolution and 100 MS/s sampling rate, which is well suited for high-resolution detectors as Silicon, HPGe or inorganic scintillators like NaI or CsI coupled with Charge Sensitive Preamplifiers. In the waveform recording mode, algorithms of zero suppression are also implemented to reduce the data throughput. The acquisition can be channel independent and it is possible to make coincidence/anti-coincidence logic among different channels and external veto/gating. Multiple boards can be synchronized to build up complex systems.

In the case of DPP mode, data can be saved in time-stamped list mode to support higher input rates and improve the throughput performances. Piled-up events can be rejected or saved for offline analysis. The acquisition in DPP-PHA mode is fully controlled by the CoMPASS and MC2Analyzer software, which manage the algorithm parameters, build the plots and saves the relevant energy and time spectra. In the case of waveform recording mode, the user can take advantage of the CAENScope and WaveDump software to access and save the waveforms. For DPP-DAW mode, a c demo fully controls the acquisition, data plotting and saving.

Libraries and demo software in C and LabView are available for integration and customization of specific acquisition systems.

The DT5724 comes in a Desktop form factor with 2 or 4 input channels. The communication to and from the board is provided through USB and Optical Link interfaces.

Technical Specifications

GENERAL

Weight: 680 g
Form Factor: 154x50x164 mm3 (WxHxD) Desktop

ANALOG INPUT

Channels: 2/4 channels single-ended
Impedance: 50 Ω
Bandwidth: 40 MHz
Connector: MCX
Full-Scale Range: 2.25 Vpp (default) 0.5 Vpp and 10 Vpp (on request)
Offset: Programmable DAC for DC offset adjustment in the full range
Abs Max Rating: @2.25 Vpp: 6 Vpp (with Vrail max +6 V or –6 V for any DAC offset value)

DIGITAL CONVERSION

Resolution: 14 bits
Sampling Rate: 100 MS/s simultaneously on each channel
16.1 MS/s minimum by hardware down-sampling (see AN6308)
781 kS/s minimum by firmware decimation (Waveform recording firmware only)

SYSTEM PERFORMANCES

ENOB: 11.89 (64 kS Buffer)
SINAD: 73.85 dB
THD: 87.8 dB
SFDR: 93.5 dB
SIGMA: 1.09 LSB rms (64 kS buffer, open input)

ADC CLOCK GENERATION

Clock source: internal/external
Onboard programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference

DIGITAL I/O
CLK-IN (AMP Modu II)
– AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by CAEN adapter)
– Jitter <100 ppm requested
GPO (LEMO)
General purpose digital output
NIM/TTL, Rt = 50 Ω

GPI (LEMO)

General purpose digital input
NIM/TTL, Zin = 50 Ω
TRG-IN (LEMO)
External trigger digital input
NIM/TTL, Zin = 50 Ω
ACQUISITION MEMORY
  • 512 kS/ch (5 ms @ 100 MS/s) or 4 MS/ch (40 ms @ 100 MS/s) Multi Event Buffer divisible into 1 ÷ 1024 buffers
  • Independent read and write access
  • Programmable event size and pre/post-trigger
TRIGGER
Trigger Source
– Self-trigger: channel over/under threshold for either Common or Individual (DPP only) trigger generation
– External-trigger: Common by TRG-IN connector
– Software-trigger: Common by software command
Trigger Time Stamp
– Waveform Recording: 31-bit counter, 20 ns resolution, 21 s range; 48-bit extension by firmware
– DPP-PHA: 30-bit counter, 10 ns resolution, 64-bit extension by software
– DPP-DAW: 31-bit counter, 10 ns resolution, 21 s range; 64-bit extension by software)
Trigger Propagation
GPO digital output
SYNCHRONIZATION
Clock Propagation
One-to-many: clock distribution from DT4700 to CLK-IN connector
Acquisition Synchronization
Sync Start/Stop through digital I/O (TRG-IN input, GPO output)
Trigger Time Stamp Alignment
By GPI input connector
ADC & MEMORY CONTROLLER FPGA

One Altera Cyclone EP1C20 per channel

COMMUNICATION INTERFACE

USB: USB 2.0 compliant Transfer rate up to 30 MB/s
Optical Link: CAEN CONET proprietary protocol, up to 80 MB/s transfer rate. Daisy chainable: it is possible to connect up to 8 ADC modules to a single Optical Link Controller (Mod.A2818/A3818/A4818)

FIRMWARE
Waveform Recording Firmware
Free firmware for waveform recording
Upgrades
Firmware can be upgraded via Optical Link or USB
DPP Firmware
Paid firmware for Digital Pulse Processing: DPP-PHA, and DPP-DAW
 
SOFTWARE

Libraries: General-purpose C and LabVIEW Libraries
Configuration Tools: CAEN Upgrader for Firmware upgrade, Direct Register, Example codes
Readout Software: CAEN WaveDump, CAENScope, CoMPASS, MC2Analyzer, DPP-DAW Demo software

POWER CONSUMPTIONS

1.7 A @ 12 V (Typ.)

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Accessories

AI2700
Optical Fiber Series
A318
Adapter for Clock signal FISCHER S101A004 male to 3-pin AMPMODU IV female – 10 cm
A654
Cable assembly LEMO 00 male to MCX male – 1 m
A659
Cable assembly BNC male to MCX male – 1 m
A317
Cable assembly for Clock distribution 3-pin AMPMODU IV female terminations – 18 cm / 25cm
A4818
USB 3.0 to CONET2 Adapter
Digitizers Input Range Personalizations
Digitizers Input Range Customizations

Ordering Options

Code Description
WDT5724AXAAA DT5724A - 2 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, SE  (Obsolete)
WDT5724DXAAA DT5724D - 4 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, SE  (Obsolete)
WDT5724EXAAA DT5724E - 2 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C4, SE  (Obsolete)
WDT5724XAAAA DT5724 - 4 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C4, SE  (Obsolete)
WDT5724BXAAA DT5724B - 4 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C20, SE   RoHS
WDT5724CXAAA DT5724C - 2 Ch. 14 bit 100 MS/s Digitizer: 512kS/ch, C20, SE   RoHS
WDT5724FXAAA DT5724F - 4 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, SE   RoHS
WDT5724GXAAA DT5724G - 2 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch, C20, SE   RoHS

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