N6751

16 general purpose LVDS I/O controlled by the FPGA: Run, Busy, Veto, Trigger and other functions can be programmed
An Input Pattern from the LVDS I/O can be associated to each trigger as an event marker

Firmware can be upgraded via VMEbus or Optical Link

General purpose C libraries, configuration tools, readout software (Windows® and Linux® support), LabVIEW™ VIs and demos for Windows® only

5.6 A @ +5V; 250 mA @ +12V, -12V not used

Form Factor
1-unit wide NIM

Weight
870 g

Channels
2/4 channels single-ended

Impedance
50 Ω

Bandwidth
500 MHz

Connector
MCX

Full-Scale Range
1 Vpp (default); 0.2 Vpp (on request)

Offset
Programmable DAC for DC
offset adjustment in the full range

Abs Max Rating
@1 Vpp: 3 Vpp (with Vrail max +3 V or –3 V for any DAC offset value)
@200 mVpp: 2 Vpp (with Vrail max +2 V or –2 V for any DAC offset value)

Resolution
10 bits

Sampling Rate
1 GS/s (2 GS/s in DES mode)
Simultaneously on each channel
250 MS/s minimum by hardware down-sampling (see AN6308)

• ENOB: 9.04 (56 kS Buffer)

• SINAD: 56.19 dB

• THD: 70.2 dB

• SFDR: 79.7 dB

• SIGMA: 0.58 LSB rms (56 kS buffer, open input)

• Clock source: internal/external

• Onboard programmable PLL provides generation of the main board clocks from an internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference

CLK-IN (AMP Modu II)
AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by CAEN adapter)
Jitter < 100 ppm requested

GPO (LEMO)
General purpose digital output
NIM/TTL, Rt = 50 Ω

GPI (LEMO)
General purpose digital input
NIM/TTL, Zin = 50 Ω

TRG-IN (LEMO)
External trigger digital input
NIM/TTL, Zin = 50 Ω

1.835 MS/ch (1.9 ms @ 1GS/s) or 3.6 MS/ch in DES mode (1.9 ms @ 2GS/s); 14.4 MS/ch (15 ms @ 1 GS/s) or 28.8 MS/ch in DES mode (15 ms @ 2 GS/s) divisible into 1 ÷ 1024 buffers
Independent read and write access
Programmable event size and pre/post-trigger

Trigger Source
Self-trigger: channel over/under threshold for either Common or Individual (DPP only) trigger generation
External-trigger: Common by TRG-IN connector
Software-trigger: Common by software command

Trigger Propagation
GPO digital output

Trigger Time Stamp
Waveform Recording: 31-bit counter, 16 ns resolution, 17 s range; 48-bit extension by firmware
DPP-PSD: 48-bit counter, 1 ns resolution, 78 h range; 10-bit and 1 ps fine time stamp with digital CFD
DPP-ZLEplus: 31-bit counter, 16 ns resolution, 17 s range; 48-bit extension by firmware

Clock Propagation
One-to-many: clock distribution from DT4700 to CLK-IN connector

Acquisition Synchronization
Sync Start/Stop through digital I/O (TRG-IN input, GPO output)

Trigger Time Stamp Alignment
By GPI input connector

Two Altera Cyclone EP3C16 (one FPGA serves 2 channels)