Obsolete

N6740D

32 Channel 12bit 62.5 MS/s Digitizer

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Home Modular Pulse Processing ElectronicsAnalogDigitizers N6740D

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Highlights

12 bit 62.5 MS/s ADC
32 channels (16 channels on LEMO connectors using A746D adapter)
ERNI SMC Dual Row 68 pin connector (32 channels)
2 Vpp single ended input range
16-bit programmable DC offset adjustment: ±1 V
Trigger Time stamps
Memory buffer: 192 kS/ch, up to 1024 events
FPGA for real-time data processing:
- Digital Charge to Digital Converter (DPP-QDC)
Programmable event size and pre-post trigger adjustment
Optical Link interface (CAEN proprietary protocol)
USB2.0 interface
Firmware upgradeable via USB/Optical Link
Libraries, Demos (C and LabView) and Software tools for Windows and Linux

Overview

The N6740D is a 32ch 12 bit 62.5 MS/s (65 MS/s using external clock) NIM Waveform Digitizer with 2 Vpp single ended input dynamics on a ERNI SMC connector. 32 channels can be available on LEMO connectors using the A746D adapter.
The DC offset adjustment (range ±1 V) by a programmable 16bit DACs (one for each 8-channel group) allows a right sampling of a bipolar (Vin = ±1 V) up to a full positive (Vin = 0 ÷ +2 V) or negative (Vin= 0 ÷ -2 V) analog input swing without losing dynamic resolution.

The module features a front panel Clock Input and a PLL for clock synthesis from internal/external references. The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read by USB or Optical Link. The acquisition can continue without dead time in a new buffer.

Each channel has a SRAM Multi-Event Buffer of 192 kS divisible into 1 ÷ 1024 buffers of programmable size. The readout (by USB or Optical Link) of a frozen buffer is independent from the write operations in the active circular buffer (ADC data storage).
N6740D supports multi-board synchronization allowing all ADCs to be synchronized to a common clock source and ensuring Trigger time stamps alignment. Once synchronized, all data will be aligned and coherent across multiple N6740 boards.

The trigger signal can be provided externally via the front panel Trigger Input as well as via the software, but it can also be generated internally thanks to threshold self-trigger capability.

N6740D houses USB 2.0 and Optical Link interfaces. USB 2.0 allows data transfers up to 30 MB/s. The Optical Link supports transfer rate of 80 MB/s and offers Daisy chain capability. Therefore, it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod. A2818).

Software available (Windows and Linux):
CAEN provides drivers for all the different types of physical communication channels, a set of C and LabView libraries (CAENComm and CAENDigitizer), demo applications and utilities:

CAENUpgrader: tool that allows the user to update the firmware of the digitizers, change the PLL settings, load, when requested, the license for the pay firmware and other utilities.

Standard Firmware compliant:

CAEN WaveDump: software console application that can be used to configure and readout event data from any model of the CAEN digitizer family and save the data into a memory buffer allocated for this purpose.

Digital Pulse Processing firmware for Physics Applications – this special firmware allows to perform on-line processing on detector signal directly digitizer:

DPP-QDC Pulse Processing for Charge to Digital Converter DT5740D digitizer running DPP-QDC firmware becomes a digital replacement of Single Gate QDC plus Discriminator and Gate Generator.
CoMPASS Multiparametric Acquisition Software.

Ordering Options

Code	Description
WN6740DXAAAA	N6740D – 32 Ch. 12 bit 62.5 MS/s Digitizer: 192kS/ch, EP3C40, SE (Obsolete)	RoHS

Code

Description

WN6740DXAAAA

N6740D – 32 Ch. 12 bit 62.5 MS/s Digitizer: 192kS/ch, EP3C40, SE

(Obsolete)

RoHS

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Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	VX2730	VME64X	32	500	250	[0.2 ÷ 4]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1725 / V1725S	VME	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT2745	Desktop	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New R5560	rack mount 19 -2U	128+6	125	60	2	14	max. 8k	RJ45	n. a.	YES
	New DTL2730	Desktop	8	500	TBD	TBD	14	TBD	MCX	DPP-PHA(cs), DPP-PSD(cs), D-SCOPE(cs)	YES
	V1761	VME	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-WAVE	NO
	DT5751	Desktop	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	DT5725 / DT5725S	Desktop	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1724	VME64X	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW	NO
	DT5761	Desktop	1	4000	1000	1	10	7.2 M	MCX	D-WAVE	NO
	VX2745	VME64X	64	125	20	[0.4 ÷ 4]	16	21 M	2mm 40-pin header male	D-SCOPE, DPP-PHA, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5724	Desktop	4 / 2	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	DT5730 / DT5730S	Desktop	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX2740	VME64X	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, D-SCOPE, DPP-PSD, DPP-ZLEplus<sup>(cs)</sup>	YES
	V1724	VME	8	100	40	0.5 / 2.25 / 10	14	512 k / 4 M	MCX	DPP-PHA, DPP-DAW, D-WAVE	NO
	VX1761	VME64X	2	4000	1000	1	10	7.2 M / 57.6 M	MCX	D-SCOPE	NO
	DT2740	Desktop	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	V2740	VME	64	125	50	2	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	New DT2751	Desktop	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	V1730 / V1730S	VME	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	N6725 / N6725S	NIM	8	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	New VX2751	VME64X	16	1000	500	[0.2 ÷ 2]	14	84 M	MCX	DPP-PHA, DPP-PSD, D-SCOPE<sup>(cs)</sup>	YES
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	V2745	VME	64	125	20	[0.04 + 4]	16	21 M	2mm 40-pin header male	DPP-PHA, DPP-PSD, D-SCOPE, DPP-ZLEplus<sup>(cs)</sup>	YES
	DT5742	Desktop	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	VX1725 / VX1725S	VME64X	8 / 16	250	125	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	VX1730 / VX1730S	VME64X	8 / 16	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V2730B	VME64	16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE(cs)	YES
	N6730 / N6730S	NIM	8	500	250	0.5 - 2	14	640 k / 5.12 M	MCX	DPP-PHA, DPP-PSD, DPP-ZLEplus, DPP-DAW, D-WAVE	NO
	V1743	VME	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	VX1751	VME64X	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1720	VME	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1751	VME	2(DES mode) - 4	2000(DES mode) - 1000	500	0.2 / 1	10	3.6 M(DES mode) - 1.8 M / 28.8 M(DES mode) - 14.4 M	MCX	DPP-PSD, DPP-ZLEplus, D-WAVE	NO
	VX1742	VME64X	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT5743	Desktop	8	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	DT5720	Desktop	4 / 2	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	V1742	VME	32 + 2	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO
	DT2730	Desktop	32 / 16	500	250	[0.2 ÷ 4]	14	MCX	84 M	DPP-PHA, DPP-PSD, D-SCOPE	YES
	VX1743	VME64X	16	3200 (Based on SAMLONG chip: 3.2 GS/s Switched Capacitor Array)	500	2.5	12	0.007 M	MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	New DTL2751	Desktop	4	1000	TBD	TBD	14	MCX	TBD	DPP-PSD(cs), D-SCOPE(cs)	YES
	VX1720	VME64X	8	250	125	2	12	1.25 M / 10 M	MCX	DPP-PSD, D-WAVE	NO
	N6742	NIM	16 + 1	5000 (Based on DRS4 chip: 5 GS/s Switched Capacitor Array)	500	1	12	0.128 / 1	MCX	D-WAVE	NO

Image	Name	Package	No. of Channels	Max Sampling Rate (MS/s)	Bandwidth (MHz)	Full Scale Range (V)	Resolution (bits)	Board Memory (Samples/ch)	Analog Input Connectors	CAEN firmware	Open FPGA
	VX1740D	VME64X	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO
	V1740	VME	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	VX1740	VME64X	64	62.5	30	2 / 10	12	192 k / 1.5 M	SMC 68P	D-WAVE	NO
	DT5740D	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	DPP-QDC,D-WAVE	NO
	DT5740	Desktop	32(SMC conn.) - 16(MCX conn)	62.5	30	2 / 10	12	192 k	SMC 68P - MCX	D-WAVE	NO
	V1740D	VME	64	62.5	30	2 / 10	12	192 k	SMC 68P	DPP-QDC, D-WAVE	NO


Package	Form Factor: 1-unit wide NIM module Weight: 870 g
Analog Input	32 channels (ERNI SMC Dual Row 68pin connector) or 16 channels (LEMO connectors) by A746D adapter Single-ended input range: 2 Vpp Bandwidth: 30 MHz Programmable DAC for Offset Adjustment (one for each 8-channel group): ±1 V Absolute max. input voltage: 6 Vpp with Vrail max. to +6V or -6V for any DAC offset value
Digital Conversion	Resolution: 12 bit Sampling rate: up to 62.5 MS/s simultaneously on each channel (65 MS/s using external clock)
System Performance	ENOB: SINAD: THD: 11.20 (48 kS Buffer) 69.20 dB 87.10 dB SFDR: SIGMA: 94.9 dB 0.50 LSB rms (48 kS Buffer, open input)
ADC Sampling Clock generation	Supports three operating modes: PLL mode: internal reference (62.5 MHz local oscillator) PLL mode: external reference on CLK_IN PLL Bypass mode: external clock on CLK_IN drives directly ADC clocks (Freq.: 10 ÷ 65 MHz)
Digital I/O	CLK_IN (AMP Modu II): – AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML(single ended NIM/TTL available by custom cable) – Jitter <100 ppm TRG_IN (LEMO 50 Ohm, NIM/TTL): external trigger input GPI/GPO (LEMO 50 Ohm, NIM/TTL): programmable front panel input/output
Memory Buffer	192 kS/ch Multi Event Buffer Programmable event size and pre-post trigger Divisible into 1 ÷ 1024 buffers Readout of Frozen buffer independent from write operations in the active buffer (ADC data storage)
Common Trigger	External (signal on TRG_IN) Software (by USB or Optical Link) Self trigger (internal threshold self-trigger generated by each 8-channel group)
Trigger Time Stamp	31-bit counter, 16 ns resolution, 17 s range^() ^()Trigger Logic and Trigger Time Stamp counter operate at 125 MHz (i.e. 8 ns or 1/2 ADC clock cycles), while the counter value is read at a frequency of 62.5 MHz (i.e. 16 ns).
ADC and Memory controller FPGA	One Altera Cyclone EP3C40 per 16 channel
Multi Modules Synchronization	Clock distribution: by Fan Out Trigger distribution: by Daisy chain or Fan Out Time stamp synchronization
Optical Link	CAEN CONET proprietary protocol Up to 80 MB/s transfer rate Daisy‐chain: it is possible to connect up to 8 or 32 ADC modules to a single Optical Link Controller (respectively A2818/A4818 or A3818/A5818)
USB interface	USB2.0 compliant Up to 30 MB/s transfer rate
Upgrade	Firmware can be upgraded via Optical Link or USB interface
Software	CoMPASS Multiparametric Acquisition Software Caen DPP-QDC demo software (windows only) with C source file for developers

N6740D

32 Channel 12bit 62.5 MS/s Digitizer

Highlights

Overview

Software

CAEN Toolbox

CAENComm Library

CAENDigitizer Library

COMPASS

WAVEDUMP2

DPP-QDC

Firmware

D-WAVE

Accessories

A4818

A317

A746D

A371

AI2700

A654

A659

Ordering Options

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