32 Channel Multievent Individual Gate QDC
- Individual Gate input per channel
- 0 ÷ 400 pC input range
- Full 12-bit resolution
- 100 fC LSB
- 5.7 µs / 32 ch conversion time
- 32 event buffer memory
- 600 ns fast clear time
- Zero and overflow suppression for each channel
- ±0.1% integral non linearity
- ±1.5% differential non linearity
- BLT32/MBLT64/CBLT32/CBLT64 data transfer
- Multicast commands
- Live insertion
- Libraries, Demos (C and LabView) and Software tools for Windows and Linux
The Model V862 is a 1-unit wide VME 6U module housing 32 Charge-to-Digital Conversion channels with current integrating negative inputs. Each channel has an independent gate input (GATE i) logically ANDed with a COMMON GATE input; the input charge on the i-th channel is converted to a voltage level by a QAC (Charge to Amplitude Conversion) section when both the GATE i and COMMON GATE signal are active. Input range is 0 ÷ 400 pC.
The integral non linearity is ±0.1% of full scale range (FSR), measured from 2% to 97% of FSR; the differential non linearity is ±1.5% of FSR, measured from 3% to 100% of FSR.
The ADCs use a sliding scale technique to reduce the differential non-linearity.
The outputs of the QAC sections are multiplexed and subsequently converted by two fast 12-bit ADCs (5.7 µs for 32 channels).
The Mod. V862 offers a 32 event buffer memory; programmable zero suppression and trigger counter complete the features of the unit. The module works in A24/A32 mode. The data transfer occurs in D16, D32, BLT32, MBLT64 or CBLT32/CBLT64 mode. The unit also supports the Multicast commands.
The board has a special circuitry that allows it to be removed from and inserted in a powered crate without switching the crate off.
6U-high, 1U-wide VME unit (version AA requires the V430 backplane)
- Input signals
32 channels, 50 Ohm impedance, negative polarity, DC coupling
- Individual gates
32 differential ECL signals
- Full scale
(if Sliding Scale is used FSR is reduced to 3840 counts)
- Max. Tolerated positive voltage input
< 5% (with 2 ns fall time input pulses)
- RMS Noise
0.5 counts typical
- Input offset
- Integral non linearity
±0.1% of FSR (=3840 counts)
- Interchannel gain uniformity
- Interchannel Isolation
> 60 dB
- Power rejection
0.002 count/mV (+5V); 0.01 count/mV (-5V)
0.0046 count/mV (+12V); 0.0012 count/mV (-12V)
- Fast clear time
- Common Gate timing
The Common Gate signal must precede the analog input by > 15 ns
- Individual Gate timing
the Individual Gate signal must precede the analog input by > 8 ns
- Conversion time
5.7 µs for all channels
- Zero suppression
Treshold values programmable in:
16 ADC counts steps over the entire FSR
2 ADC counts steps over 1/8 of FSR
- COMMON GATE input
input signal, common to all channels, acting as the temporal window within which the individually gated inputs are integrated.
NIM signals, high impedance
- Control inputs
active-high, differential ECL input signals:
GATE: same function as COMMON GATE NIM input
RST: resets QAC sections, MEB status and control registers
VETO: inhibits the conversion of the QAC signals
FCLR: FAST CLEAR of QAC sections.
- Control outputs
differential ECL output signals:
DRDY: indicates the presence of data
BUSY: board full, resetting, converting or in MEMORY TEST mode
- VME interface
Compare with QDCs.
|WV862XACAAAA||V862AC - 32 Channel Multievent Charge ADC With Individual Gate (No JAUX, live ins)|