CAEN Readout System for Multiplexed Signals
- Readout System for Multiplexed Signals coming from ASIC chip as Amplex, Gassiplex, VA and others
- Based on V1495 and V1724 running dedicated firmware
- Each V1495 can house up to three A395D Sequencer
- Each V1724 can handle up to 8 ASIC chains
- Zero suppression with individual threshold setting
- Programmable clock skew to compensate the increasing delay of the clock propagating through the ASIC chains
The requirement of including an analog multiplexer in some detector acquisition chain comes from the huge number of independent channels that have to be handled. Considering for instance the case of the silicon detector used as vertex tracker, the number of single independent channels is typically very high, in the order of hundreds or thousands of channels. Providing an ADC for each single channel would simply cost too much. A completely different approach has to implemented. In a new scenario, the signal coming from the different detector channels will be pipelined in a single analog signal in which the whole information is collected: the pulse height (proportional to the charge and so to the energy released by the interacting particle) of the single channel. A not negligible acquisition dead time is the unavoidable compromise when using this kind of solution.
The CAEN Readout System for Multiplexed Signals is designed to manage the data readout from multiplexed ASIC chips (like Amplex, Gassiplex, VA and others) commonly used as front end electronics in Nuclear and Particle Physics whenever a large number of channels is required.
The system is able to provide all the relevant signals needed by the ASICs and to sample their multiplexed output following a precise time pattern according to the readout sequence.
The old-fashioned solution proposed in the past by CAEN and worldwide recognized as a standard was based on two VME modules: the V551 (in several versions) that in response to an external trigger that produce different pilot signals for the multiplexing chip(s) (Clock, Track & Hold, Clear) and the V550 that acquired the analog stream coming from the chip(s), digitize one single point per channels, perform a programmable pedestal subtraction, and matches the recorded value to the original channel. Moreover the V550 implemented a Zero Suppression algorithm using a programmable threshold in order to reduce the data throughput. Both the modules have become obsolete, difficult and expensive to produce and not up to date with the new CAEN data acquisition technology based on digitizers.
The new CAEN Readout System for Multiplexed Signals is based on two CAEN VME boards, V1495 and V1724, running dedicated firmware FW1495CRAMS and DPP-CRAMS. The V1495 is a general purpose board in which has been implemented a sequencer whose outputs (Track & Hold, Clock and Clear) are generated in LVDS and replicated (NIM or TTL levels) on a piggyback A395D (8 NIM/TTL input/output channels piggyback). The V1495 is provided with three free slots that can house the A395D. The sequencer receives an external trigger and starts the conversion sequence by synchronizing the V1724 ADC board. V1724 is an 8 channels, 14-bit ADC. Receiving a start signal from one of the A395D housed in V1495, V1724 can handle the readout of the multiplexed signals coming from the ASICs according to the programmed sequence. Each V1724 input channel can handle an entire chain of several ASIC chips: one V1724 can manage up to 8 ASIC chains i.e. up to 16384 multiplexed channels. V1724 can also perform an effective Zero Suppression allowing the user to set an individual threshold for each multiplexed channel. Moreover, a programmable clock skew is available to compensate the increasing delay that affects the clock propagation through the ASIC chains in order to reach an higher readout rate.