| Packaging |
1-unit wide 6U VME module |
| Inputs |
8 channels, 50 Ohm impedance, negative polarity, DC coupling |
| Input range |
Dual range: 0 ÷ 900 pC / 0÷100 pC |
| Resolution |
12 bit (15 bit dynamics) |
| Gain |
High range: 200 fC/count; Low range: 25 fC/count |
| Max. tolerated positive voltage input |
15 mV |
| Reflections |
< 5% with 2 ns fall time input signals |
| Input offset |
±2 mV |
| RMS Noise |
0.5 counts typical |
| Integral non linearity |
0.1% of FSR (=3840 counts)
from 5% to 95% of FSR |
| Interchannel gain uniformity |
±4% |
| Interchannel gain uniformity |
> 60 dB |
| Power rejection |
0.002 count/mV (+5V); 0.01 count/mV (-5V)
0.0046 count/mV (+12V); 0.0012 count/mV (-12V) |
| Fast clear time |
600 ns |
| Gate timing |
the Gate signal must precede the analog input by > 15 ns |
| Conversion time |
2.8 µs for all channels |
| Zero suppression |
Treshold values programmable in:
16 ADC counts steps over the entire FSR
2 ADC counts steps over 1/8 of FSR |
| Control inputs |
NIM input signals:
GATE: temporal window for current integration .
RST: resets QAC sections, MEB status and control registers.
VETO: inhibits the conversion of the QAC signals.
FCLR: FAST CLEAR of QAC sections. |
| Control outputs |
NIM output signals:
DRDY: indicates the presence of data
BUSY: board full, resetting, converting or in MEMORY TEST mode |
| VME interface |
A24/A32
Geographical Addressing
Multicast commands
D16/D32,BLT32/MBLT64,CBLT32/CBLT64 |
