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| Highlights |
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- 8 channel
- 14 bit 100 MS/s ADC
- 2.25 Vpp Input dynamics (single ended or differential); 10Vpp & 500mVpp single ended also available
- Analog Sum/Majority and digital over/under threshold flags for Global Trigger logic
- Front panel clock In/Out available for multiboard synchronisation (direct feed through or PLL based synthesis)
- 16 programmable LVDS I/Os
- Trigger Time stamps
- Memory buffer: up to 4 MSample/ch
- FPGA for real-time data processing
- Zero Suppression and Data Reduction algorithms
- Programmable event size and pre-post trigger adjustment
- VME64X compliant interface
- Optical Link interface
- A2818 PCI controller available for handling up to 8 Modules daisy chained via Optical Link
- Firmware upgradeable via VME/Optical Link
- Libraries, Demos (C and LabView) and Software tools for Windows and Linux
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The Mod. V1724 is a 1-unit wide VME 6U module housing a 8 Channel 14 bit 100 MS/s Flash ADC Waveform Digitizer with threshold Auto-Trigger capabilities.
Input dynamics is 2.25 Vpp (single ended or differential); 10Vpp and 500mVpp single ended is also available.
The DC offset of the input signal can be adjusted channel per channel by a programmable 16bit DAC on single ended input version.
The modules feature a front panel clock/reference In/Out and a PLL for clock synthesis from internal/external references. This allows multi board phase synchronizations to an external clock reference or to a clock Digitizer master board.
The data stream is continuously written in a circular memory buffer. When the trigger occurs, the FPGA writes further N samples for the post trigger and freezes the buffer that can be read either via VME or via Optical Link. The acquisition can continue without dead time in a new buffer.
Each channel has a SRAM memory buffer (4Msamples/ch) with independent read-write access divided in buffers of programmable size (1 ÷ 1024). “Zero suppression” and “data reduction” algorithms allow substantial savings in data amount readout and processing, rejecting samples smaller than programmable thresholds.
The trigger signal can be provided via the front panel input as well as via the VMEbus, but it can also be generated internally. The trigger from one board can be propagated to the other boards through the front panel Trigger Output.
An Analog Output allows to reproduce the sum of the input signals as well as the majority of the buffer occupancy.
The Modules VME interface is VME64X compliant and the data readout can be performed in Single Data Transfer (D32), 32/64 bit Block Transfer (BLT, MBLT, 2eVME, 2eSST) and 32/64 bit Chained Block Transfer (CBLT).
The boards houses a daisy chainable Optical Link able to transfer data at 80 MB/s, thus it is possible to connect up to eight ADC boards (64 ADC channels) to a single Optical Link Controller (Mod. A2818). Optical Link and VME access are internally arbitrated.
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| Package |
1-unit wide VME 6U module |
| Analog Input |
8 channels, single-ended (SE) or differential.
Input range 2.25Vpp (10Vpp and 500mVpp SE on request).
Bandwidth: 40MHz; Programmable DAC for Offset Adjust x ch (SE only). |
| Digital Conversion |
Resolution: 14 bit; Sampling rate: 10 to 100 MS/s simultaneously on each channel; multi board synchronization (one board can act as clock master).
External Gate Clock capability (NIM/TTL) for burst or single sampling mode. |
| ADC Sampling Clock generation |
Three operating modes:
- PLL mode - internal reference (50 MHz loc. oscillator).
- PLL mode - external reference on CLK_IN (Jitter<100ppm).
- PLL Bypass mode: Ext. clock on CLK_IN drives directly ADC clocks (Freq.: 10 ÷ 100MHz). |
| CLK_IN |
AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available using CAEN cable). |
| CLK_OUT |
DC coupled differential LVDS output clock, locked to ADC sampling clock. Freq.: 10 ÷ 100MHz. |
| Memory Buffer |
512K sample/ch or 4M sample/ch; Multi Event Buffer with independent read and write access. Programmable event size and pre-post trigger. Divisible into 1 ÷ 1024 buffers. |
| Trigger |
Common External TRGIN (NIM or TTL) and VME CommandIndividual channel autotrigger (time over/under threshold)TRGOUT (NIM or TTL) for the trigger propagation to other V1724 boards. |
| Trigger Time Stamp |
32bit – 10ns (43s range). Sync input for Time Stamp alignment. |
| ADC and Memory controller FPGA |
One Altera Cyclone EP1C4 or EP1C20 per channel. |
Optical Link
(not available on Mod. V1724LC) |
Data readout and slow control with transfer rate up to 80 MB/s, to be used instead of VME bus. Daisy chainable: one A2818 PCI card can control and read eight V1724 boards in a chain. |
| VME interface |
VME64X compliant
D32, BLT32, MBLT64, CBLT32/64, 2eVME, 2eSST, Multi Cast CyclesTransfer rate: 60MB/s (MBLT64), 100MB/s (2eVME), 160MB/s (2eSST).
Sequential and random access to the data of the Multi Event Buffer. The Chained readout allows to read one event from all the boards in a VME crate with a BLT access. |
| Upgrade |
V1724 firmware can be upgraded via VME or Optical Link |
| Software |
General purpose C Libraries and Demo Programs (CAENScope). |
Analog Monitor
(not available in V1724LC) |
12bit / 100MHz DAC FPGA controlled output, five operating modes:
Test Waveform: 1 Vpp test ramp generator
Majority: MON/Σ output signal is proportional to the number of channels (enabled) under/over threshold (1 step = 125mV)
Linear SUM: MON/Σ output signal provides the linear sum of the (enabled) channels (1 Vpp)
Buffer Occupancy: MON/Σ output signal is proportional to the Multi Event Buffer Occupancy
Voltage level: MON/Σ output signal is a programmable voltage level |
| LVDS I/O |
16 gen. purpose LVDS I/O controlled by FPGA
Busy, Data Ready, Memory full, Individual Trig-Out and other function can be programmed.
An Input Pattern from the LVDS I/O can be associated to each trigger as an event marker. |
| Input connectors |
Single ended: MCX
Differential: Tyco MODU II |
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Compare with other
ADCs (Sampling)
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Model |
Package |
Function |
Description |
Compare
All / Reset |
| Code |
Description |
| WPERS0172401 |
V1724 Customization - 10Vpp Input Range, SE |
| WA654K4AAAAA |
A654 KIT4 - 4 MCX TO LEMO Cable Adapter |
| WA654K8AAAAA |
A654 KIT8 - 8 MCX TO LEMO Cable Adapter |
| WV1724FXAAAA |
V1724F - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch,C20, DIFF |
| WV1724EXAAAA |
V1724E - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch,C20, SE |
| WV1724DXAAAA |
V1724D - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch,C4, DIFF |
| WV1724CXAAAA |
V1724C - 8 Ch. 14 bit 100 MS/s Digitizer: 512KS/ch, C4, DIFF |
| WV1724BXAAAA |
V1724B - 8 Ch. 14 bit 100 MS/s Digitizer: 4MS/ch,C4, SE |
| WV1724XAAAAA |
V1724 - 8 Ch. 14 bit 100 MS/s Digitizer: 512KS/ch,C4, SE |
| WA654XAAAAAA |
A654 - Single Channel MCX to LEMO Cable Adapter |
| WA2818XAAAAA |
A2818 - PCI Optical Link |
| WAY2705XAAAA |
AY2705 - Optical Fibre 5 m. duplex |
| WAY2720XAAAA |
AY2720 - Optical Fibre 20 m. duplex |
| WAY2730XAAAA |
AY2730 - Optical Fibre 30 m. duplex |
| WAI2730XAAAA |
AI2730 - Optical Fibre 30 m. simplex |
| WAI2720XAAAA |
AI2720 - Optical Fibre 20 m. simplex |
| WAI2705XAAAA |
AI2705 - Optical Fibre 5 m. simplex |
| WAI2703XAAAA |
AI2703 - Optical Fibre 30cm. simplex |
| WV1724GXAAAA |
V1724G - 8 Ch. 14 bit 100 MS/s Digitizer: 512KS/ch, C20, SE |
| WPERS0172402 |
V1724 Customization - 500mVpp Input Range, SE |
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| © 2000 - 2010 CAEN S.p.A. All rights reserved. |
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