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| Highlights |
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- 21 bit resolution
- 25 ps LSB
- 52 µs full scale range
- ECL/LVDS Input Signals
- 5 ns Double Hit Resolution
- Trigger Matching and Continuous Storage acquisition modes
- Leading and/or Trailing Edge detection
- 32 k x 32 bit output buffer
- BLT32/MBLT64/CBLT32/CBLT64 cycles supported
- Multicast commands
- Live Insertion
- Libraries, Demos (C and LabView) and Software tools for Windows and Linux
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The Mod. V1290A is a 1-unit wide VME 6U module that houses 32 independent Multi Hit/Multi Event Time to Digital Conversion channels. The unit houses 4 High Performance TDC chips, developed by CERN. LSB is 25 ps (21 bit resolution, 52 µs FSR). The module accepts both ECL and LVDS inputs.
The channels can be enabled for the detection of hits rising/falling edges or for their width measurement. For each channel there is a digital adjustment for the zero-ing of any offsets. The data acquisition can be programmed in "EVENTS" ("TRIGGER MATCHING MODE", with a programmable time window) or in "CONTINUOUS STORAGE MODE". Both ECL and LVDS input signals are supported.
The module programming is performed via a microcontroller that implements a high-level user friendly interface. The VME interface allows the module to work in A24 and A32 addressing modes. The board houses a 32 k x 32 bit deep Output Buffer, that can be readout via VME in a completely independent way from the acquisition itself. The internal registers are available in D16 mode only, while the Output Buffer is accessible in D32, BLT32 or MBLT64. The module supports also the Chained Block Transfer mechanism and the Multicast commands.
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| Packaging |
6U-high, 1U-wide VME unit |
| Inputs |
32 ECL/LVDS, 110 Ohm impedance |
| Double hit resolution |
5 ns |
| Acquisition modes |
Trigger Matching Mode; Continuous Storage Mode |
| Built-in memory |
32 kwords deep Output Buffer |
| Trigger Window Width |
Programmable from 25 ns to 100 µs |
| Dynamic Range |
52 µs |
| LSB |
25 ps |
| RMS resolution |
< 35 ps (typical) |
| Integral non linearity |
< 2.5 LSB |
| Differential non linearity |
< 3 LSB |
| Interchannel Isolation |
≤ 3 LSB |
| Offset spread |
< 2 ns |
| EXT TRIGGER input |
Two LEMO 00 bridged connectors, ECL signal, 110 Ohm |
| Clock source |
Internal (40 MHz) or External (on Control connector), dip switch selectable |
| Control inputs |
active-high, differential ECL input signals:
RST: resets Output Buffer, Status and Control registers.
CLR: FAST CLEAR of TAC sections rising-edge active,
differential ECL input signals:
CLK: external clock
TRG: trigger for the TDC latching |
| Control outputs |
differential ECL output signal:
OUT_PROG: control output signal, programmable via the out prog control register |
| Displays |
DTACK: green LED; lights up at each VME access.
PWR: green/red LED; green: power ON, red: failure status.
TERM: green LED; control bus termination ON.
FULL: red LED; memory full. ERROR: red LED; TDC global error.
DRDY: yellow LED; at least one datum in the output buffer |
| VME |
Addressing modes: A24, A32, MCST
Data transfer modes: D16, D32, BLT32, BLT64, CBLT Readout rate: 33 Mb/s |
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Compare with other
TDCs
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Model |
Package |
Function |
Description |
Compare
All / Reset |
| Code |
Description |
| WV1290AEXAAA |
V1290A - 32 Ch. Multievent Multihit TDC 25 psec ECL/LVDS (no JAUX) |
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| © 2000 - 2010 CAEN S.p.A. All rights reserved. |
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