

Packaging |
Desktop module; 154x50x164 mm3 (WxHxD), Weight: 680 gr |
Analog Input |
4 channels (MCX 50 Ohm) Single-ended Input range: 2 Vpp; Bandwidth: 125 MHz. Programmable DAC for Offset Adjust x ch., adjustment range: ±1V |
Digital Conversion |
Resolution: 12 bit; Sampling rate: 10 to 250 MS/s simultaneously on each channel; multi board synchronization |
ADC Sampling Clock generation |
Three operating modes: - PLL mode - internal reference (50 MHz loc. oscillator). - PLL mode - external reference on CLK_IN (Jitter<100ppm). - PLL Bypass mode: Ext. clock on CLK_IN drives directly ADC clocks (Freq.: 10 ÷ 250 MHz). |
Digital I/O |
CLK_IN (AMP Modu II): - AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available ) - Jitter<100ppm TRG_IN (LEMO 50 Ohm, NIM/TTL) GPI/GPO (LEMO 50 Ohm, NIM/TTL) |
Memory Buffer |
1.25 M sample/ch Multi Event Buffer Programmable event size and pre-post trigger. Divisible into 1 ÷ 1024 buffers. Readout of Frozen buffer independent from write operations in the active buffer (ADC data storage). |
Trigger |
Common Trigger - TRG_IN (External signal) - Software (from USB or Optical Link) - Self trigger (Internal threshold auto-trigger) Daisy chain trigger propagation among boards (using GPO) |
Trigger Time Stamp |
32bit – 8ns (34s range) |
Multi Modules Synchronization |
Allows data alignment and consistency across multiple DT5720 modules: - CLK_IN allows the synchronization to a common clock source - GPI ensures Trigger time stamps and start acquisition times alignment |
USB interface |
USB2.0 compliant Up to 30 MB/s transfer rate |
Optical Link |
CAEN proprietary protocol, up to 80 MB/s transfer rate, Daisy chainable: it is possible to connect up to 8/32 ADC modules to a single Optical Link Controller (Mod. A2818/A3818). |
Upgrade |
Firmware can be upgraded via Optical Link or USB interface |
Software |
General purpose C and LabView Libraries Demo and Software Tools for Windows and Linux |
Electrical Power |
Voltage range: 12 ± 10% Vdc |