V775 - V785 - V792 - V862 Firmware Revision Revision 9.2 ------------- VMEbus may respond also to D32 Interrupt Cycles. Revision 9.1 ------------- Timing upgrade. Revision 9.0 ------------- Timing upgrade. Revision 8.9 ------------ Fixed the following bugs: Sometimes a Software Clear causes an error in the header of the subsequent event written in the buffer (the numer of words of the event itself was wrong). The Fast Clear Window Register has 10 bits, but only 9 can be used. Revision 8.8 ------------ Fixed the following bugs: Synchronisation read and write pointer of the events in the buffer problems with very fast CPUs. Revision 8.1 ------------ Removed some noise problems. Revision 6.2 ------------ Feature added in order to correct the data loss during the BLT and CBLT readout caused by the CPU equipped with the TUNDRA CHIPS: such chips require that during a DMA an even number of LWORD (32 bit) is transferred on the VME bus. If a BERR interrupts the DMA when an odd number of LWORD is transferred, the TUNDRA chip does not transfer the last word on the PCI bus and the datum is lost. The CONTROL REGISTER is added with one bit (64BIT_ALIGN): at power on is 0 and the behaviour of the board is the "standard" one. If this bit is set to 1, during a BLT32 an even number of LWORD is always transferred, by adding a DUMMY LWORD when necessary. In CBLT32, the DUMMY LWORD is added only by the last board. Fixed the following bugs: During the readout in CBLT64 if the number of words of the event of the LAST board is odd, the 64 bit alignment does not take place by adding “not valid data”, but the Header of the subsequent. If the BLKEND is enabled (bit 2 of CONTROL 2 register), the EOB of an event can not be read out in D32. Revision 5.1 ------------ Added the following feature: the bit 8 (STEP_TH) of the bitset2/bitclear2 register allows to set the thresholds with either steps of 16 (default) or steps of 2 (programmable up to 512). Fixed the following bug: A problem in the Output Buffer addressing is fixed. Revision 5.0 ------------ Fixed the following bug: During a CBLT readout with very fast CPUs, sometimes the board remains purged at the end of a CBLT. If a GATE is sent after a FAST CLEAR, the software reads the Header and then the Channel 1 (instead of Channel 0) Revision 4.3 ------------ Fixed the following bug: In BLT64 the data sometimes can change after the DTACK leading edge. Revision 4.2 ------------ The Iped register (offset 0x1060) at power on is initialised at 180, instead of 0. Revision 4.1 ------------ Fixed the following bug: some CPUs perform “fake” DMAs, setting the AS true after each datum transfer (it looked like the CBLTs were made by one datum per time); the IACKIN and the IACKOUT do not not follow the CPU cycles. Revision 4.0 ------------ Fixed the following bugs: The access to some module register causes the loss of the data memorised in the Output Buffer . By setting EMPTY_PROG=1 (bit 12 of the Bit Set 2 Register), the Board writes empty events into the buffer when the module becomes FULL.