Welcome
| Package |
1-unit wide VME64X module; Weight: 520 gr |
| Analog Input |
Channels 32 channels 2 special channel (TR0, TR1) Single ended Impedance Zin = 50 Ohm Connector MCX Full Scale Range (FSR) 1 Vpp Bandwidth 500 Mhz Offset Programmable 16-bit DAC for DC offset adjustment on each channel. Range ± 1 V |
| TR0 TR1 Input | MCX 50 Ohm, NIM/TTL For fast local trigger (TR0 for ch0..15, TR1 for ch16..31) and high resolution timing reference |
| Digital Conversion |
Resolution 12 bits Switched Capacitor Array Domino Ring Sampler chip (DRS4), 8+1 channels with 1024 storage cells each Sampling Rate 5 GS/s - 2.5 GS/s - 1 GS/s - 0.75 GS/s SW selectable, simultaneously on each channel Dead Time (A/D Conversion) 110 μs, analog inputs only 181 μs, digitizing TR0 |
| ADC Sampling Clock generation |
Clock source: internal/external. On-board programmable PLL provides generation of the main board clocks from internal (50 MHz local Oscillator) or external (front panel CLK-IN connector) reference Hz local Oscillator) or external (front panel CLK-IN connector) reference |
| Digital I/O |
CLK-IN (AMP Modu II) AC coupled differential input clock LVDS, ECL, PECL, LVPECL, CML (single ended NIM/TTL available by A318 adapter) Jitter < 100 ppm requested TRG-IN (LEMO) External trigger digital input NIM/TTL Zin = 50 Ohm CLK-OUT (AMP Modu II) DC coupled differential LVDS clock output locked at ADC sampling clock TRG-IN (LEMO) Trigger digital output NIM/TTL Zin = 50 Ohm S-IN (LEMO) SYNC/START front panel digital input NIM/TTL Zin =50 Ohm |
| ADC and Memory controller FPGA | Altera Cyclone EP3C16 (one FPGA manages 16+1 channels) |
| Memory | 128 events/ch or 1024 events/ch (1024 S/event) Multievent Buffer Independent read and write access; programmable event size and pre/post-trigger |
| Trigger |
Trigger Source - Fast (Low Latency) trigger: Common trigger by programmable threshold on TR0 - Self-trigger: Common trigger by combination of channels over/under threshold in logic OR - External-trigger: Common trigger by TRG IN connector - Software-trigger: Common trigger by software command Trigger Propagation TRG-OUT programmable digital output Trigger Time Stamp 30-bit counter 8.5 ns resolution 9 s range |
| LVDS I/O | 16 general purpose LVDS I/O controlled by the FPGA: Busy, Data Ready, Memory full, Individual Trig-Out and other functions can be programmed. An Input Pattern from the LVDS I/O can be associated to each trigger as an event marker |
| Communication Interface |
Optical Link CAEN CONET proprietary protocol Up to 80 MB/s transfer rate Daisy-chain: it is possible to connect up to 8 or 32 ADC modules to a single Optical Link Controller (respectively A2818 or A3818) VME VME 64X compliant Data transfer mode: BLT32, MBLT64 (70 MB/s using CAEN Bridge), CBLT32/64, 2eVME, 2eSST (up to 200 MB/s) |
| Synchronization |
Clock Propagation Daisy chain: through CLK-IN/CLK-OUT connectors One-to-many: clock distribution from an external clock source on CLK-IN connector Acquisition Synchronization Sync, Start/Stop through digital I/O (S-IN or TRG-IN input / TRG-OUT output) Trigger Time Stamps Alignment By S-IN input connector |
| Upgrade | Firmware can be upgraded via VMEbus/Optical Link |
| Software | General purpose C libraries, configura on tools, readout so ware (Windows and Linux support) |
| Power Consumption | 5.5 A @ +5V; 200 mA @ +12V, 300 mA @ -12V |
| Description | Release | Date | OS-Version | Environment | Download |
|---|---|---|---|---|---|
| Firmware CONET2 Compliant | |||||
x742 Waveform Recording FW |
4.13_1.01 | January, 2017 | |||
| FW Package 1.75 MB - Type: .cfa |
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| Release Notes 6.5 KB - Type: .txt |
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x742 Waveform Recording FW Beta Version(*) |
4.14_1.01 | July, 2017 | |||
| FW Package 1.75 MB - Type: .cfa |
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| Release Notes 7.61 KB - Type: .txt |
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| Related Models | ||
| Family | Name | Description |
|---|---|---|
| Digitizer Software | CAEN WaveDump | CAEN Digitizer readout application |
| Digitizer Software | CAENDigitizer Library | Library of functions for CAEN Digitizers high level management |
| Digitizer Software | CAENUpgrader | Firmware Upgrade Tool for Front-end Boards Bridges & VME Power Supply |
| Code | Description |
|---|---|
| WVX1742XAAAA | VX1742 - 32+2 Ch. 12 bit 5GS/s Switched-CapacitorDigitizer: 128 events/ch (1kS/event), EP3C16, SE |
| WVX1742BXAAA | VX1742B - 32+2 Ch. 12 bit 5GS/s Switched-CapacitorDigitizer: 1024 events/ch (1kS/event), EP3C16, SE |
| Manuals | Last Update |
|---|---|
| UM4279 - V1742 & VX1742 User Manual | January 27th, 2017 |
| GD5695 - 742 Quick Start Guide | January 5th, 2017 |
| UM5698 - 742 Registers Description | January 26th, 2017 |
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